[Webkit-unassigned] [Bug 168527] New: Improve ARM64 disassembler handling of pseudo ops, unsupported opcodes and zero reg

[bugzilla-daemon at webkit.org]

https://bugs.webkit.org/show_bug.cgi?id=168527

            Bug ID: 168527
           Summary: Improve ARM64 disassembler handling of pseudo ops,
                    unsupported opcodes and zero reg
    Classification: Unclassified
           Product: WebKit
           Version: WebKit Nightly Build
          Hardware: Unspecified
                OS: Unspecified
            Status: NEW
          Severity: Normal
          Priority: P2
         Component: JavaScriptCore
          Assignee: webkit-unassigned at lists.webkit.org
          Reporter: msaboff at apple.com

There are several minor issues with the ARM64 disassemble's ability to handle the code we currently generate.  The list includes:
 - Integer extract and rotate immediate opcodes aren't disassembled.
 - Single source bit operations like CLZ, CLS and REV aren't disassembled.
 - The conditional instructions like CSEL, CSINC, CSET and FCSEL aren't disassembled.
 - There are many opcode where we print X31/W31 instead of XZR/WZR for the zero register.
 - For register index load and store instruction, we print the zero register when the convention is that we should omit.
 - Several pseudo instructions are handled
   MVN Xd, Xn in place of ORN Xd, XZR, Xn
   LSL Xd, Xn, #count in place of UBFIZ Xd, Xn, #count, #count
   SMULL Xd, Wn, Wm in place of SMADDL Xd, Wn, Wm, XZR

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