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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - Improve ARM64 disassembler handling of pseudo ops, unsupported opcodes and zero reg"
href="https://bugs.webkit.org/show_bug.cgi?id=168527">168527</a>
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<th>Summary</th>
<td>Improve ARM64 disassembler handling of pseudo ops, unsupported opcodes and zero reg
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<th>Classification</th>
<td>Unclassified
</td>
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<th>Product</th>
<td>WebKit
</td>
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<th>Version</th>
<td>WebKit Nightly Build
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<th>Hardware</th>
<td>Unspecified
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<th>OS</th>
<td>Unspecified
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<th>Status</th>
<td>NEW
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<th>Severity</th>
<td>Normal
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<th>Priority</th>
<td>P2
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<th>Component</th>
<td>JavaScriptCore
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<th>Assignee</th>
<td>webkit-unassigned@lists.webkit.org
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<th>Reporter</th>
<td>msaboff@apple.com
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<pre>There are several minor issues with the ARM64 disassemble's ability to handle the code we currently generate. The list includes:
- Integer extract and rotate immediate opcodes aren't disassembled.
- Single source bit operations like CLZ, CLS and REV aren't disassembled.
- The conditional instructions like CSEL, CSINC, CSET and FCSEL aren't disassembled.
- There are many opcode where we print X31/W31 instead of XZR/WZR for the zero register.
- For register index load and store instruction, we print the zero register when the convention is that we should omit.
- Several pseudo instructions are handled
MVN Xd, Xn in place of ORN Xd, XZR, Xn
LSL Xd, Xn, #count in place of UBFIZ Xd, Xn, #count, #count
SMULL Xd, Wn, Wm in place of SMADDL Xd, Wn, Wm, XZR</pre>
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