[Webkit-unassigned] [Bug 98694] [Performance] Speed-up DOM tree traversal on ARM platforms

bugzilla-daemon at webkit.org bugzilla-daemon at webkit.org
Fri Nov 9 10:57:26 PST 2012


--- Comment #27 from Kulanthaivel Palanichamy <kulanthaivel at codeaurora.org>  2012-11-09 10:59:03 PST ---
(In reply to comment #26)
> (In reply to comment #25)
> > I think we need a lot of more sample than just one computer. If we're enabling this on x86 processors, I'd like to see samples on following architectures:
> > 
> > AMD: K8 (was one of the most popular processor lines for AMD), K10 (still used in many laptops), Turion or Fusion, and Bulldozer.
> > 
> > Intel: Nehalem or Westmere (there still quite few NetBurst architectures CPUs), original Core, Core 2, and Sandy Bridge.
> > 
> > Quite frankly, the variation of cache size, bus speed, branch prediction mechanisms and accuracy etc... between these architectures is so large that I'm highly skeptical that this optimization is helpful on the average for x86.
> If remember correctly prefetch is a NOP operation on Intel chips because it used to be an AMD-only extension (until AMD64), but it does help on AMD chips and is part of x86-64/amd64.

It could be true for Intel's legacy architectures, but from Pentium III onwards, it seems like they have implemented PREFETCH completely. Even then, among their PIII, Core2, Sandy Bridge and other recent architectures, they have many variations in their implementation like prefetch cache level, prefetch cache line size, etc..

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