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        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - [jsc][mips] study whether using SYNC_MB for memoryFence/storeFence works and improves performances"
   href="https://bugs.webkit.org/show_bug.cgi?id=169984">169984</a>
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        </tr>

        <tr>
          <th>Summary</th>
          <td>[jsc][mips] study whether using SYNC_MB for memoryFence/storeFence works and improves performances
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>WebKit
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>Other
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>Other
          </td>
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        <tr>
          <th>OS</th>
          <td>Linux
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>Normal
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>P2
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>JavaScriptCore
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>webkit-unassigned&#64;lists.webkit.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>guijemont&#64;igalia.com
          </td>
        </tr></table>
      <p>
        <div>
        <pre>For MacroAssemblerMIPS::memoryFence() and ::storeFence(), we use a sync instruction with SYNC (0) in the stype field. We should check whether the optional SYNC_MB (0x10) stype can work for our needs. It is defined as forcing the order of memory accesses, but unlike SYNC, SYNC_MB does not require all older instructions to be completed when the sync instruction completes, but only that they reach the load/store ordering point before the sync instruction completes, which is a slightly lighter constraint that should still be good enough for us, while potentially having a lower performance hit.</pre>
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