[Webkit-unassigned] [Bug 249040] New: [WebAssembly SIMD] Vector XOR instructions fail SIMDLane assertion on Intel

[bugzilla-daemon at webkit.org]

https://bugs.webkit.org/show_bug.cgi?id=249040

            Bug ID: 249040
           Summary: [WebAssembly SIMD] Vector XOR instructions fail
                    SIMDLane assertion on Intel
           Product: WebKit
           Version: WebKit Nightly Build
          Hardware: Unspecified
                OS: Unspecified
            Status: NEW
          Severity: Normal
          Priority: P2
         Component: WebAssembly
          Assignee: webkit-unassigned at lists.webkit.org
          Reporter: d_degazio at apple.com
            Blocks: 246345

We use vector XOR in a variety of places in AirIRGenerator to clear a vector value, since XOR is the easiest way to clear/zero a vector on Intel. In some of these places, we create a VectorXor instruction with the SIMDLane of the larger operation. This is often incorrect, however, since vector XOR is only meant to operate over vectors with lane type v128, and passing a different lane type trips an assertion in the macro assembler. In these places, we should explicitly provide a SIMDLane of v128 when constructing the Air instruction.


Referenced Bugs:

https://bugs.webkit.org/show_bug.cgi?id=246345
[Bug 246345] [SIMD] Intel support
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