[Webkit-unassigned] [Bug 112886] [SH4] LLInt sh4 backend implementation

[bugzilla-daemon at webkit.org]

https://bugs.webkit.org/show_bug.cgi?id=112886





--- Comment #10 from Filip Pizlo <fpizlo at apple.com>  2013-03-23 20:43:09 PST ---
(In reply to comment #8)
> Another thing that I do not understand inside risc.rb is the riscLowerShiftOps, where:
> # lshifti foo, bar
> #
> # will become:
> #
> # andi foo, 31, tmp
> # lshifti tmp, bar
> 
> This potentially adds a useless opcode (when foo < 32), and worst, this can lead to an incorrect behaviour. For instance:
> 
> lshifti 33, register
> 
> will become
> 
> and 33, 31, tmp
> lshifti tmp, register
> 
> So we'll left-shift register by 1 (because 33 & 31 = 1), and I don't think this is what we expect here, right?

It's necessary for ARM since that processor treats shiftAmount >= 32 to mean that the result is zeroed. If risc.rb is emitting the 'and' even when the operand is an immediate that is within range, then you should file a bug. 

If SH4 doesn't need the shifts then you don't need to run that phase.

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