[Webkit-unassigned] [Bug 106739] Fix the atomicIncrement implementation for MIPS GCC

[bugzilla-daemon at webkit.org]

https://bugs.webkit.org/show_bug.cgi?id=106739





--- Comment #10 from Balazs Kilvady <kilvadyb at homejinni.com>  2013-01-24 02:06:20 PST ---
(In reply to comment #9)
> (From update of attachment 184191 [details])
> This looks amazingly inefficient for an atomic increment/decrement. Is there seriously no better solution for MIPS?
Thank you for reviewing.

32 bit MIPS cores have a ll/sc instruction pair to implement atomic read-modify-write. But only for 32 bit values in memory. Only on 64 bit cores there is a lld/scd pair for 64 memory-values. We haven't found a way to ensure atomicity on 32 bit cores without locking.

This patch is only for 64-bit atomics on 32 bit MIPS cores, and that 32-bit's atomics are inlined efficiently
by the toolchain. When webkit compiled for mips64, then we do have 64-bit atomic-ops as well by gcc, but those instructions are not available on the 32-bit cores.

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