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<dt>Revision</dt> <dd><a href="http://trac.webkit.org/projects/webkit/changeset/286892">286892</a></dd>
<dt>Author</dt> <dd>mikhail@igalia.com</dd>
<dt>Date</dt> <dd>2021-12-10 17:17:19 -0800 (Fri, 10 Dec 2021)</dd>
</dl>

<h3>Log Message</h3>
<pre>[JSC][32bit] Add callee save registers for MIPS
https://bugs.webkit.org/show_bug.cgi?id=233766

Reviewed by Mark Lam.

This patch enables callee save registers for mips, which fixes an
assertion violation from the call frame shufflers in some tests if
jsc was built with assertions enabled (either debug or release+assert
mode).

* jit/RegisterSet.cpp:
(JSC::RegisterSet::llintBaselineCalleeSaveRegisters):
(JSC::RegisterSet::dfgCalleeSaveRegisters):</pre>

<h3>Modified Paths</h3>
<ul>
<li><a href="#trunkSourceJavaScriptCoreChangeLog">trunk/Source/JavaScriptCore/ChangeLog</a></li>
<li><a href="#trunkSourceJavaScriptCorejitRegisterSetcpp">trunk/Source/JavaScriptCore/jit/RegisterSet.cpp</a></li>
</ul>

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<div id="patch">
<h3>Diff</h3>
<a id="trunkSourceJavaScriptCoreChangeLog"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/ChangeLog (286891 => 286892)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/ChangeLog    2021-12-11 01:10:47 UTC (rev 286891)
+++ trunk/Source/JavaScriptCore/ChangeLog       2021-12-11 01:17:19 UTC (rev 286892)
</span><span class="lines">@@ -1,3 +1,19 @@
</span><ins>+2021-12-10  Mikhail R. Gadelha  <mikhail@igalia.com>
+
+        [JSC][32bit] Add callee save registers for MIPS
+        https://bugs.webkit.org/show_bug.cgi?id=233766
+
+        Reviewed by Mark Lam.
+
+        This patch enables callee save registers for mips, which fixes an
+        assertion violation from the call frame shufflers in some tests if
+        jsc was built with assertions enabled (either debug or release+assert
+        mode).
+
+        * jit/RegisterSet.cpp:
+        (JSC::RegisterSet::llintBaselineCalleeSaveRegisters):
+        (JSC::RegisterSet::dfgCalleeSaveRegisters):
+
</ins><span class="cx"> 2021-12-10  Yusuke Suzuki  <ysuzuki@apple.com>
</span><span class="cx"> 
</span><span class="cx">         [JSC] isTaggedJSCCodePtrImpl does not have proper implementation for JITCage & JITCode combination
</span></span></pre></div>
<a id="trunkSourceJavaScriptCorejitRegisterSetcpp"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/jit/RegisterSet.cpp (286891 => 286892)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/jit/RegisterSet.cpp  2021-12-11 01:10:47 UTC (rev 286891)
+++ trunk/Source/JavaScriptCore/jit/RegisterSet.cpp     2021-12-11 01:17:19 UTC (rev 286892)
</span><span class="lines">@@ -213,7 +213,7 @@
</span><span class="cx">     result.set(GPRInfo::regCS5);
</span><span class="cx">     result.set(GPRInfo::regCS6);
</span><span class="cx"> #endif
</span><del>-#elif CPU(ARM_THUMB2)
</del><ins>+#elif CPU(ARM_THUMB2) || CPU(MIPS)
</ins><span class="cx">     result.set(GPRInfo::regCS0);
</span><span class="cx">     result.set(GPRInfo::regCS1);
</span><span class="cx"> #elif CPU(ARM64) || CPU(RISCV64)
</span><span class="lines">@@ -223,9 +223,6 @@
</span><span class="cx">     static_assert(GPRInfo::regCS9 == GPRInfo::notCellMaskRegister, "");
</span><span class="cx">     result.set(GPRInfo::regCS8);
</span><span class="cx">     result.set(GPRInfo::regCS9);
</span><del>-#elif CPU(MIPS)
-    result.set(GPRInfo::regCS0);
-    result.set(GPRInfo::regCS1);
</del><span class="cx"> #else
</span><span class="cx">     UNREACHABLE_FOR_PLATFORM();
</span><span class="cx"> #endif
</span><span class="lines">@@ -253,7 +250,7 @@
</span><span class="cx">     result.set(GPRInfo::regCS5);
</span><span class="cx">     result.set(GPRInfo::regCS6);
</span><span class="cx"> #endif
</span><del>-#elif CPU(ARM_THUMB2)
</del><ins>+#elif CPU(ARM_THUMB2) || CPU(MIPS)
</ins><span class="cx">     result.set(GPRInfo::regCS0);
</span><span class="cx">     result.set(GPRInfo::regCS1);
</span><span class="cx"> #elif CPU(ARM64)
</span><span class="lines">@@ -261,7 +258,6 @@
</span><span class="cx">     static_assert(GPRInfo::regCS9 == GPRInfo::notCellMaskRegister, "");
</span><span class="cx">     result.set(GPRInfo::regCS8);
</span><span class="cx">     result.set(GPRInfo::regCS9);
</span><del>-#elif CPU(MIPS)
</del><span class="cx"> #else
</span><span class="cx">     UNREACHABLE_FOR_PLATFORM();
</span><span class="cx"> #endif
</span></span></pre>
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