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<dl class="meta">
<dt>Revision</dt> <dd><a href="http://trac.webkit.org/projects/webkit/changeset/284179">284179</a></dd>
<dt>Author</dt> <dd>commit-queue@webkit.org</dd>
<dt>Date</dt> <dd>2021-10-14 11:06:10 -0700 (Thu, 14 Oct 2021)</dd>
</dl>

<h3>Log Message</h3>
<pre>[RISCV64] Support logical operations with immediates on BaseIndex addresses in LLInt
https://bugs.webkit.org/show_bug.cgi?id=231734

Patch by Zan Dobersek <zdobersek@igalia.com> on 2021-10-14
Reviewed by Yusuke Suzuki.

RISCV64 offlineasm implementation gains support for performing logical
operations with immediate values on BaseIndex adresses, fixing the build
and bringing things back into operational state.

For this to function properly, BaseIndex loading is reworked so that no
additional scratch register is necessary for computing the target
address.

* offlineasm/riscv64.rb:</pre>

<h3>Modified Paths</h3>
<ul>
<li><a href="#trunkSourceJavaScriptCoreChangeLog">trunk/Source/JavaScriptCore/ChangeLog</a></li>
<li><a href="#trunkSourceJavaScriptCoreofflineasmriscv64rb">trunk/Source/JavaScriptCore/offlineasm/riscv64.rb</a></li>
</ul>

</div>
<div id="patch">
<h3>Diff</h3>
<a id="trunkSourceJavaScriptCoreChangeLog"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/ChangeLog (284178 => 284179)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/ChangeLog    2021-10-14 18:05:03 UTC (rev 284178)
+++ trunk/Source/JavaScriptCore/ChangeLog       2021-10-14 18:06:10 UTC (rev 284179)
</span><span class="lines">@@ -1,3 +1,20 @@
</span><ins>+2021-10-14  Zan Dobersek  <zdobersek@igalia.com>
+
+        [RISCV64] Support logical operations with immediates on BaseIndex addresses in LLInt
+        https://bugs.webkit.org/show_bug.cgi?id=231734
+
+        Reviewed by Yusuke Suzuki.
+
+        RISCV64 offlineasm implementation gains support for performing logical
+        operations with immediate values on BaseIndex adresses, fixing the build
+        and bringing things back into operational state.
+
+        For this to function properly, BaseIndex loading is reworked so that no
+        additional scratch register is necessary for computing the target
+        address.
+
+        * offlineasm/riscv64.rb:
+
</ins><span class="cx"> 2021-10-14  Commit Queue  <commit-queue@webkit.org>
</span><span class="cx"> 
</span><span class="cx">         Unreviewed, reverting r284151.
</span></span></pre></div>
<a id="trunkSourceJavaScriptCoreofflineasmriscv64rb"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/offlineasm/riscv64.rb (284178 => 284179)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/offlineasm/riscv64.rb        2021-10-14 18:05:03 UTC (rev 284178)
+++ trunk/Source/JavaScriptCore/offlineasm/riscv64.rb   2021-10-14 18:06:10 UTC (rev 284179)
</span><span class="lines">@@ -214,7 +214,7 @@
</span><span class="cx">             $asm.puts "#{instruction} #{operands[1].riscv64Operand}, #{operands[0].riscv64Operand}"
</span><span class="cx">         end
</span><span class="cx">     when [BaseIndex, RegisterID]
</span><del>-        operands[0].riscv64Load(RISCV64ScratchRegister.x31, RISCV64ScratchRegister.x30)
</del><ins>+        operands[0].riscv64Load(RISCV64ScratchRegister.x31)
</ins><span class="cx">         $asm.puts "#{instruction} #{operands[1].riscv64Operand}, 0(x31)"
</span><span class="cx">     else
</span><span class="cx">         riscv64RaiseMismatchedOperands(operands)
</span><span class="lines">@@ -241,7 +241,7 @@
</span><span class="cx">             $asm.puts "#{instruction} #{operands[0].riscv64Operand}, #{operands[1].riscv64Operand}"
</span><span class="cx">         end
</span><span class="cx">     when [RegisterID, BaseIndex]
</span><del>-        operands[1].riscv64Load(RISCV64ScratchRegister.x31, RISCV64ScratchRegister.x30)
</del><ins>+        operands[1].riscv64Load(RISCV64ScratchRegister.x31)
</ins><span class="cx">         $asm.puts "#{instruction} #{operands[0].riscv64Operand}, 0(x31)"
</span><span class="cx">     when [Immediate, Address]
</span><span class="cx">         $asm.puts "li x30, #{operands[0].riscv64Operand}"
</span><span class="lines">@@ -252,7 +252,7 @@
</span><span class="cx">             $asm.puts "#{instruction} x30, #{operands[1].riscv64Operand}"
</span><span class="cx">         end
</span><span class="cx">     when [Immediate, BaseIndex]
</span><del>-        operands[1].riscv64Load(RISCV64ScratchRegister.x31, RISCV64ScratchRegister.x30)
</del><ins>+        operands[1].riscv64Load(RISCV64ScratchRegister.x31)
</ins><span class="cx">         $asm.puts "li x30, #{operands[0].riscv64Operand}"
</span><span class="cx">         $asm.puts "#{instruction} x30, 0(x31)"
</span><span class="cx">     else
</span><span class="lines">@@ -400,7 +400,7 @@
</span><span class="cx">         end
</span><span class="cx">         $asm.puts "#{instruction} x30, x31, #{operands[2].asmLabel}"
</span><span class="cx">     when [RegisterID, BaseIndex, LocalLabelReference]
</span><del>-        operands[1].riscv64Load(RISCV64ScratchRegister.x31, RISCV64ScratchRegister.x30)
</del><ins>+        operands[1].riscv64Load(RISCV64ScratchRegister.x31)
</ins><span class="cx">         $asm.puts "#{riscv64LoadInstruction(size)} x31, 0(x31)"
</span><span class="cx">         signExtendForSize(operands[0], 'x30', size)
</span><span class="cx">         $asm.puts "#{instruction} x30, x31, #{operands[2].asmLabel}"
</span><span class="lines">@@ -507,7 +507,7 @@
</span><span class="cx">         signExtendForSize('x31', size)
</span><span class="cx">         $asm.puts "#{bInstruction} x31, #{operands[2].asmLabel}"
</span><span class="cx">     when [BaseIndex, LocalLabelReference]
</span><del>-        operands[0].riscv64Load(RISCV64ScratchRegister.x31, RISCV64ScratchRegister.x30)
</del><ins>+        operands[0].riscv64Load(RISCV64ScratchRegister.x31)
</ins><span class="cx">         $asm.puts "#{loadInstruction} x31, 0(x31)"
</span><span class="cx">         $asm.puts "#{bInstruction} x31, #{operands[1].asmLabel}"
</span><span class="cx">     else
</span><span class="lines">@@ -874,6 +874,17 @@
</span><span class="cx">         else
</span><span class="cx">             $asm.puts "#{storeInstruction} x30, #{operands[1].riscv64Operand}"
</span><span class="cx">         end
</span><ins>+    when [Immediate, BaseIndex]
+        operands[1].riscv64Load(RISCV64ScratchRegister.x31)
+        $asm.puts "#{loadInstruction} x30, 0(x31)"
+        if operands[0].riscv64RequiresLoad
+            $asm.puts "li x31, #{operands[0].riscv64Operand}"
+            $asm.puts "#{instruction} x30, x30, x31"
+            operands[1].riscv64Load(RISCV64ScratchRegister.x31)
+        else
+            $asm.puts "#{instruction}i x30, x30, #{operands[0].riscv64Operand}"
+        end
+        $asm.puts "#{storeInstruction} x30, 0(x31)"
</ins><span class="cx">     else
</span><span class="cx">         riscv64RaiseMismatchedOperands(operands)
</span><span class="cx">     end
</span><span class="lines">@@ -967,7 +978,7 @@
</span><span class="cx">             $asm.puts "#{loadInstruction} #{operands[1].riscv64Operand}, #{operands[0].riscv64Operand}"
</span><span class="cx">         end
</span><span class="cx">     when [BaseIndex, FPRegisterID]
</span><del>-        operands[0].riscv64Load(RISCV64ScratchRegister.x31, RISCV64ScratchRegister.x30)
</del><ins>+        operands[0].riscv64Load(RISCV64ScratchRegister.x31)
</ins><span class="cx">         $asm.puts "#{loadInstruction} #{operands[1].riscv64Operand}, 0(x31)"
</span><span class="cx">     else
</span><span class="cx">         riscv64RaiseMismatchedOperands(operands)
</span><span class="lines">@@ -984,7 +995,7 @@
</span><span class="cx">             $asm.puts "#{storeInstruction} #{operands[0].riscv64Operand}, #{operands[1].riscv64Operand}"
</span><span class="cx">         end
</span><span class="cx">     when [FPRegisterID, BaseIndex]
</span><del>-        operands[1].riscv64Load(RISCV64ScratchRegister.x31, RISCV64ScratchRegister.x30)
</del><ins>+        operands[1].riscv64Load(RISCV64ScratchRegister.x31)
</ins><span class="cx">         $asm.puts "#{storeInstruction} #{operands[0].riscv64Operand}, 0(x31)"
</span><span class="cx">     else
</span><span class="cx">         riscv64RaiseMismatchedOperands(operands)
</span><span class="lines">@@ -1434,14 +1445,18 @@
</span><span class="cx"> end
</span><span class="cx"> 
</span><span class="cx"> class BaseIndex
</span><del>-    def riscv64Load(target, scratch)
</del><ins>+    def riscv64Load(target)
</ins><span class="cx">         case riscv64OperandTypes([base, index])
</span><span class="cx">         when [RegisterID, RegisterID]
</span><del>-            $asm.puts "slli #{target.riscv64Operand}, #{index.riscv64Operand}, #{scaleShift}"
-            $asm.puts "add #{target.riscv64Operand}, #{base.riscv64Operand}, #{target.riscv64Operand}"
</del><span class="cx">             if offset.value != 0
</span><del>-                $asm.puts "li #{scratch.riscv64Operand}, #{offset.value}"
-                $asm.puts "add #{target.riscv64Operand}, #{target.riscv64Operand}, #{scratch.riscv64Operand}"
</del><ins>+                $asm.puts "li #{target.riscv64Operand}, #{offset.value >> scaleShift}"
+                $asm.puts "add #{target.riscv64Operand}, #{target.riscv64Operand}, #{index.riscv64Operand}"
+                $asm.puts "slli #{target.riscv64Operand}, #{target.riscv64Operand}, #{scaleShift}"
+                $asm.puts "ori #{target.riscv64Operand}, #{target.riscv64Operand}, #{offset.value & ((1 << scaleShift) - 1)}"
+                $asm.puts "add #{target.riscv64Operand}, #{base.riscv64Operand}, #{target.riscv64Operand}"
+            else
+                $asm.puts "slli #{target.riscv64Operand}, #{index.riscv64Operand}, #{scaleShift}"
+                $asm.puts "add #{target.riscv64Operand}, #{base.riscv64Operand}, #{target.riscv64Operand}"
</ins><span class="cx">             end
</span><span class="cx">         else
</span><span class="cx">             riscv64RaiseMismatchedOperands([base, index])
</span><span class="lines">@@ -1730,7 +1745,7 @@
</span><span class="cx">             when [RegisterID, Immediate]
</span><span class="cx">                 $asm.puts "jr #{operands[0].riscv64Operand}"
</span><span class="cx">             when [BaseIndex, Immediate, Immediate]
</span><del>-                operands[0].riscv64Load(RISCV64ScratchRegister.x31, RISCV64ScratchRegister.x30)
</del><ins>+                operands[0].riscv64Load(RISCV64ScratchRegister.x31)
</ins><span class="cx">                 $asm.puts "ld x31, 0(x31)"
</span><span class="cx">                 $asm.puts "jr x31"
</span><span class="cx">             when [Address, Immediate]
</span><span class="lines">@@ -1859,7 +1874,7 @@
</span><span class="cx">                     $asm.puts "addi #{operands[1].riscv64Operand}, #{operands[0].base.riscv64Operand}, #{operands[0].offset.value}"
</span><span class="cx">                 end
</span><span class="cx">             when [BaseIndex, RegisterID]
</span><del>-                operands[0].riscv64Load(RISCV64ScratchRegister.x31, RISCV64ScratchRegister.x30)
</del><ins>+                operands[0].riscv64Load(RISCV64ScratchRegister.x31)
</ins><span class="cx">                 $asm.puts "mv #{operands[1].riscv64Operand}, x31"
</span><span class="cx">             when [LabelReference, RegisterID]
</span><span class="cx">                 $asm.puts "lla #{operands[1].riscv64Operand}, #{operands[0].asmLabel}"
</span></span></pre>
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