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<dt>Revision</dt> <dd><a href="http://trac.webkit.org/projects/webkit/changeset/212592">212592</a></dd>
<dt>Author</dt> <dd>msaboff@apple.com</dd>
<dt>Date</dt> <dd>2017-02-17 15:52:17 -0800 (Fri, 17 Feb 2017)</dd>
</dl>
<h3>Log Message</h3>
<pre>Improve ARM64 disassembler handling of pseudo ops, unsupported opcodes and zero reg
https://bugs.webkit.org/show_bug.cgi?id=168527
Reviewed by Filip Pizlo.
Added support for data processing 1 source instructions like rbit, rev, clz and cls.
Added support for the FP conditional select instruction, fcsel. Consolidated the
two classes for handling dmb instructions into one class. Fixed the instruction
selection mask in the integer conditional select class, A64DOpcodeConditionalSelect.
Fixed the processing of extract instruction (extr) including the rotate right (ror)
pseudo instruction. Changed the printing of x31 and w31 to xzr and wzr as operands
according to the spec. Added support for common pseudo instructions. This includes:
- mvn x1, X2 in place of orn x1, xzr, x2
- lsl x3, x4, #count in place of ubfiz x3, x4, #count, #count
- smull x5, w6, w7 in place of smaddl x5, w6, w7, XZR
- More understandable mov x8, #-304 in place of movn x8, #0x12f
- Eliminated xzr from register index loads and stores, outputing
ldr x10, [x11] instead of ldr x10, [x11, xzr]
Changed the move wide instructions to use hex literals for movz and movk.
This makes it much easier to decifer sequences of wide moves for large literals.
Before After
movz x17, #26136 movz x17, #0x6618
movk x17, #672, lsl #16 movk x17, #0x2a0, lsl #16
movk x17, #1, lsl #32 movk x17, #0x1, lsl #32
Verified that all instructions currently generated by the JSC stress tests are
disassembled.
* disassembler/ARM64/A64DOpcode.cpp:
(JSC::ARM64Disassembler::A64DOpcodeBitfield::format):
(JSC::ARM64Disassembler::A64DOpcodeDataProcessing1Source::format):
(JSC::ARM64Disassembler::A64DOpcodeDataProcessing2Source::format):
(JSC::ARM64Disassembler::A64DOpcodeDataProcessing3Source::format):
(JSC::ARM64Disassembler::A64DOpcodeExtract::format):
(JSC::ARM64Disassembler::A64DOpcodeFloatingPointConditionalSelect::format):
(JSC::ARM64Disassembler::A64DOpcodeFloatingPointIntegerConversions::format):
(JSC::ARM64Disassembler::A64DOpcodeDmb::format):
(JSC::ARM64Disassembler::A64DOpcodeLoadStoreImmediate::format):
(JSC::ARM64Disassembler::A64DOpcodeLoadStoreRegisterOffset::format):
(JSC::ARM64Disassembler::A64DOpcodeLoadStoreRegisterPair::format):
(JSC::ARM64Disassembler::A64DOpcodeLoadStoreUnsignedImmediate::format):
(JSC::ARM64Disassembler::A64DOpcodeLogicalShiftedRegister::format):
(JSC::ARM64Disassembler::A64DOpcodeMoveWide::format):
(JSC::ARM64Disassembler::A64DOpcodeDmbIsh::format): Deleted.
(JSC::ARM64Disassembler::A64DOpcodeDmbIshSt::format): Deleted.
* disassembler/ARM64/A64DOpcode.h:
(JSC::ARM64Disassembler::A64DOpcode::appendSignedImmediate64):
(JSC::ARM64Disassembler::A64DOpcode::appendUnsignedHexImmediate):
(JSC::ARM64Disassembler::A64DOpcodeDataProcessing1Source::opName):
(JSC::ARM64Disassembler::A64DOpcodeDataProcessing1Source::sBit):
(JSC::ARM64Disassembler::A64DOpcodeDataProcessing1Source::opCode):
(JSC::ARM64Disassembler::A64DOpcodeDataProcessing1Source::opCode2):
(JSC::ARM64Disassembler::A64DOpcodeDataProcessing1Source::opNameIndex):
(JSC::ARM64Disassembler::A64DOpcodeDataProcessing3Source::opName):
(JSC::ARM64Disassembler::A64DOpcodeFloatingPointConditionalSelect::opName):
(JSC::ARM64Disassembler::A64DOpcodeFloatingPointConditionalSelect::condition):
(JSC::ARM64Disassembler::A64DOpcodeDmb::option):
(JSC::ARM64Disassembler::A64DOpcodeDmb::crM):
(JSC::ARM64Disassembler::A64DOpcodeLogicalShiftedRegister::isMov):
(JSC::ARM64Disassembler::A64DOpcodeDmbIsh::opName): Deleted.
(JSC::ARM64Disassembler::A64DOpcodeDmbIshSt::opName): Deleted.</pre>
<h3>Modified Paths</h3>
<ul>
<li><a href="#trunkSourceJavaScriptCoreChangeLog">trunk/Source/JavaScriptCore/ChangeLog</a></li>
<li><a href="#trunkSourceJavaScriptCoredisassemblerARM64A64DOpcodecpp">trunk/Source/JavaScriptCore/disassembler/ARM64/A64DOpcode.cpp</a></li>
<li><a href="#trunkSourceJavaScriptCoredisassemblerARM64A64DOpcodeh">trunk/Source/JavaScriptCore/disassembler/ARM64/A64DOpcode.h</a></li>
</ul>
</div>
<div id="patch">
<h3>Diff</h3>
<a id="trunkSourceJavaScriptCoreChangeLog"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/ChangeLog (212591 => 212592)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/ChangeLog 2017-02-17 23:49:59 UTC (rev 212591)
+++ trunk/Source/JavaScriptCore/ChangeLog 2017-02-17 23:52:17 UTC (rev 212592)
</span><span class="lines">@@ -1,3 +1,68 @@
</span><ins>+2017-02-17 Michael Saboff <msaboff@apple.com>
+
+ Improve ARM64 disassembler handling of pseudo ops, unsupported opcodes and zero reg
+ https://bugs.webkit.org/show_bug.cgi?id=168527
+
+ Reviewed by Filip Pizlo.
+
+ Added support for data processing 1 source instructions like rbit, rev, clz and cls.
+ Added support for the FP conditional select instruction, fcsel. Consolidated the
+ two classes for handling dmb instructions into one class. Fixed the instruction
+ selection mask in the integer conditional select class, A64DOpcodeConditionalSelect.
+ Fixed the processing of extract instruction (extr) including the rotate right (ror)
+ pseudo instruction. Changed the printing of x31 and w31 to xzr and wzr as operands
+ according to the spec. Added support for common pseudo instructions. This includes:
+ - mvn x1, X2 in place of orn x1, xzr, x2
+ - lsl x3, x4, #count in place of ubfiz x3, x4, #count, #count
+ - smull x5, w6, w7 in place of smaddl x5, w6, w7, XZR
+ - More understandable mov x8, #-304 in place of movn x8, #0x12f
+ - Eliminated xzr from register index loads and stores, outputing
+ ldr x10, [x11] instead of ldr x10, [x11, xzr]
+
+ Changed the move wide instructions to use hex literals for movz and movk.
+ This makes it much easier to decifer sequences of wide moves for large literals.
+ Before After
+ movz x17, #26136 movz x17, #0x6618
+ movk x17, #672, lsl #16 movk x17, #0x2a0, lsl #16
+ movk x17, #1, lsl #32 movk x17, #0x1, lsl #32
+
+ Verified that all instructions currently generated by the JSC stress tests are
+ disassembled.
+
+ * disassembler/ARM64/A64DOpcode.cpp:
+ (JSC::ARM64Disassembler::A64DOpcodeBitfield::format):
+ (JSC::ARM64Disassembler::A64DOpcodeDataProcessing1Source::format):
+ (JSC::ARM64Disassembler::A64DOpcodeDataProcessing2Source::format):
+ (JSC::ARM64Disassembler::A64DOpcodeDataProcessing3Source::format):
+ (JSC::ARM64Disassembler::A64DOpcodeExtract::format):
+ (JSC::ARM64Disassembler::A64DOpcodeFloatingPointConditionalSelect::format):
+ (JSC::ARM64Disassembler::A64DOpcodeFloatingPointIntegerConversions::format):
+ (JSC::ARM64Disassembler::A64DOpcodeDmb::format):
+ (JSC::ARM64Disassembler::A64DOpcodeLoadStoreImmediate::format):
+ (JSC::ARM64Disassembler::A64DOpcodeLoadStoreRegisterOffset::format):
+ (JSC::ARM64Disassembler::A64DOpcodeLoadStoreRegisterPair::format):
+ (JSC::ARM64Disassembler::A64DOpcodeLoadStoreUnsignedImmediate::format):
+ (JSC::ARM64Disassembler::A64DOpcodeLogicalShiftedRegister::format):
+ (JSC::ARM64Disassembler::A64DOpcodeMoveWide::format):
+ (JSC::ARM64Disassembler::A64DOpcodeDmbIsh::format): Deleted.
+ (JSC::ARM64Disassembler::A64DOpcodeDmbIshSt::format): Deleted.
+ * disassembler/ARM64/A64DOpcode.h:
+ (JSC::ARM64Disassembler::A64DOpcode::appendSignedImmediate64):
+ (JSC::ARM64Disassembler::A64DOpcode::appendUnsignedHexImmediate):
+ (JSC::ARM64Disassembler::A64DOpcodeDataProcessing1Source::opName):
+ (JSC::ARM64Disassembler::A64DOpcodeDataProcessing1Source::sBit):
+ (JSC::ARM64Disassembler::A64DOpcodeDataProcessing1Source::opCode):
+ (JSC::ARM64Disassembler::A64DOpcodeDataProcessing1Source::opCode2):
+ (JSC::ARM64Disassembler::A64DOpcodeDataProcessing1Source::opNameIndex):
+ (JSC::ARM64Disassembler::A64DOpcodeDataProcessing3Source::opName):
+ (JSC::ARM64Disassembler::A64DOpcodeFloatingPointConditionalSelect::opName):
+ (JSC::ARM64Disassembler::A64DOpcodeFloatingPointConditionalSelect::condition):
+ (JSC::ARM64Disassembler::A64DOpcodeDmb::option):
+ (JSC::ARM64Disassembler::A64DOpcodeDmb::crM):
+ (JSC::ARM64Disassembler::A64DOpcodeLogicalShiftedRegister::isMov):
+ (JSC::ARM64Disassembler::A64DOpcodeDmbIsh::opName): Deleted.
+ (JSC::ARM64Disassembler::A64DOpcodeDmbIshSt::opName): Deleted.
+
</ins><span class="cx"> 2017-02-17 Zan Dobersek <zdobersek@igalia.com>
</span><span class="cx">
</span><span class="cx"> [GLib] GCActivityCallback::scheduleTimer() keeps pushing dispatch into the future
</span></span></pre></div>
<a id="trunkSourceJavaScriptCoredisassemblerARM64A64DOpcodecpp"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/disassembler/ARM64/A64DOpcode.cpp (212591 => 212592)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/disassembler/ARM64/A64DOpcode.cpp 2017-02-17 23:49:59 UTC (rev 212591)
+++ trunk/Source/JavaScriptCore/disassembler/ARM64/A64DOpcode.cpp 2017-02-17 23:52:17 UTC (rev 212592)
</span><span class="lines">@@ -83,8 +83,7 @@
</span><span class="cx"> OPCODE_GROUP_ENTRY(0x15, A64DOpcodeConditionalBranchImmediate),
</span><span class="cx"> OPCODE_GROUP_ENTRY(0x15, A64DOpcodeCompareAndBranchImmediate),
</span><span class="cx"> OPCODE_GROUP_ENTRY(0x15, A64DOpcodeHint),
</span><del>- OPCODE_GROUP_ENTRY(0x15, A64DOpcodeDmbIsh),
- OPCODE_GROUP_ENTRY(0x15, A64DOpcodeDmbIshSt),
</del><ins>+ OPCODE_GROUP_ENTRY(0x15, A64DOpcodeDmb),
</ins><span class="cx"> OPCODE_GROUP_ENTRY(0x16, A64DOpcodeUnconditionalBranchImmediate),
</span><span class="cx"> OPCODE_GROUP_ENTRY(0x16, A64DOpcodeUnconditionalBranchRegister),
</span><span class="cx"> OPCODE_GROUP_ENTRY(0x16, A64DOpcodeTestAndBranchImmediate),
</span><span class="lines">@@ -95,6 +94,7 @@
</span><span class="cx"> OPCODE_GROUP_ENTRY(0x18, A64DOpcodeLoadStoreRegisterOffset),
</span><span class="cx"> OPCODE_GROUP_ENTRY(0x19, A64DOpcodeLoadStoreUnsignedImmediate),
</span><span class="cx"> OPCODE_GROUP_ENTRY(0x1a, A64DOpcodeConditionalSelect),
</span><ins>+ OPCODE_GROUP_ENTRY(0x1a, A64DOpcodeDataProcessing1Source),
</ins><span class="cx"> OPCODE_GROUP_ENTRY(0x1a, A64DOpcodeDataProcessing2Source),
</span><span class="cx"> OPCODE_GROUP_ENTRY(0x1b, A64DOpcodeDataProcessing3Source),
</span><span class="cx"> OPCODE_GROUP_ENTRY(0x1c, A64DOpcodeLoadStoreImmediate),
</span><span class="lines">@@ -101,6 +101,7 @@
</span><span class="cx"> OPCODE_GROUP_ENTRY(0x1c, A64DOpcodeLoadStoreRegisterOffset),
</span><span class="cx"> OPCODE_GROUP_ENTRY(0x1d, A64DOpcodeLoadStoreUnsignedImmediate),
</span><span class="cx"> OPCODE_GROUP_ENTRY(0x1e, A64DOpcodeFloatingPointCompare),
</span><ins>+ OPCODE_GROUP_ENTRY(0x1e, A64DOpcodeFloatingPointConditionalSelect),
</ins><span class="cx"> OPCODE_GROUP_ENTRY(0x1e, A64DOpcodeFloatingPointDataProcessing2Source),
</span><span class="cx"> OPCODE_GROUP_ENTRY(0x1e, A64DOpcodeFloatingPointDataProcessing1Source),
</span><span class="cx"> OPCODE_GROUP_ENTRY(0x1e, A64DOpcodeFloatingFixedPointConversions),
</span><span class="lines">@@ -288,7 +289,7 @@
</span><span class="cx"> const char* const A64DOpcodeBitfield::s_extendPseudoOpNames[3][3] = {
</span><span class="cx"> { "sxtb", "sxth", "sxtw" }, { 0, 0, 0} , { "uxtb", "uxth", "uxtw" } };
</span><span class="cx"> const char* const A64DOpcodeBitfield::s_insertOpNames[3] = { "sbfiz", "bfi", "ubfiz" };
</span><del>-const char* const A64DOpcodeBitfield::s_extractOpNames[3] = { "sbfx", "bf", "ubfx" };
</del><ins>+const char* const A64DOpcodeBitfield::s_extractOpNames[3] = { "sbfx", "bfxil", "ubfx" };
</ins><span class="cx">
</span><span class="cx"> const char* A64DOpcodeBitfield::format()
</span><span class="cx"> {
</span><span class="lines">@@ -310,7 +311,7 @@
</span><span class="cx"> } else if (immediateS() == 15) {
</span><span class="cx"> appendInstructionName(extendPseudoOpNames(1));
</span><span class="cx"> isSTXType = true;
</span><del>- } else if (immediateS() == 31 && is64Bit()) {
</del><ins>+ } else if (immediateS() == 31 && is64Bit() && !opc()) {
</ins><span class="cx"> appendInstructionName(extendPseudoOpNames(2));
</span><span class="cx"> isSTXType = true;
</span><span class="cx"> }
</span><span class="lines">@@ -324,17 +325,7 @@
</span><span class="cx"> }
</span><span class="cx"> }
</span><span class="cx">
</span><del>- if (opc() == 0x2 && immediateS() == (immediateR() + 1)) {
- // lsl
- appendInstructionName("lsl");
- appendRegisterName(rd(), is64Bit());
- appendSeparator();
- appendRegisterName(rn(), is64Bit());
- appendSeparator();
- appendUnsignedImmediate((is64Bit() ? 63u : 31u) - immediateR());
-
- return m_formatBuffer;
- } else if (!(opc() & 0x1) && ((immediateS() & 0x1f) == 0x1f) && (is64Bit() == (immediateS() >> 5))) {
</del><ins>+ if (!(opc() & 0x1) && ((immediateS() & 0x1f) == 0x1f) && (is64Bit() == (immediateS() >> 5))) {
</ins><span class="cx"> // asr/lsr
</span><span class="cx"> appendInstructionName(!opc() ? "ars" : "lsr");
</span><span class="cx">
</span><span class="lines">@@ -345,23 +336,37 @@
</span><span class="cx"> appendUnsignedImmediate(immediateR());
</span><span class="cx">
</span><span class="cx"> return m_formatBuffer;
</span><del>- } else if (immediateS() < immediateR()) {
- // bit field insert
- appendInstructionName(insertOpNames());
</del><ins>+ }
</ins><span class="cx">
</span><ins>+ if (opc() == 0x2 && (immediateS() + 1) == immediateR()) {
+ // lsl
+ appendInstructionName("lsl");
</ins><span class="cx"> appendRegisterName(rd(), is64Bit());
</span><span class="cx"> appendSeparator();
</span><span class="cx"> appendRegisterName(rn(), is64Bit());
</span><span class="cx"> appendSeparator();
</span><span class="cx"> appendUnsignedImmediate((is64Bit() ? 64u : 32u) - immediateR());
</span><del>- appendSeparator();
- appendUnsignedImmediate(immediateS() + 1);
-
</del><ins>+
</ins><span class="cx"> return m_formatBuffer;
</span><del>- } else {
- // bit field extract
- appendInstructionName(extractOpNames());
</del><ins>+ }
+
+ if (immediateS() < immediateR()) {
+ if (opc() != 1 || rn() != 0x1f) {
+ // bit field insert
+ appendInstructionName(insertOpNames());
</ins><span class="cx">
</span><ins>+ appendRegisterName(rd(), is64Bit());
+ appendSeparator();
+ appendRegisterName(rn(), is64Bit());
+ appendSeparator();
+ appendUnsignedImmediate((is64Bit() ? 64u : 32u) - immediateR());
+ appendSeparator();
+ appendUnsignedImmediate(immediateS() + 1);
+
+ return m_formatBuffer;
+ }
+
+ appendInstructionName(opName());
</ins><span class="cx"> appendRegisterName(rd(), is64Bit());
</span><span class="cx"> appendSeparator();
</span><span class="cx"> appendRegisterName(rn(), is64Bit());
</span><span class="lines">@@ -368,12 +373,14 @@
</span><span class="cx"> appendSeparator();
</span><span class="cx"> appendUnsignedImmediate(immediateR());
</span><span class="cx"> appendSeparator();
</span><del>- appendUnsignedImmediate(immediateS() - immediateR() + 1);
-
</del><ins>+ appendUnsignedImmediate(immediateS());
+
</ins><span class="cx"> return m_formatBuffer;
</span><span class="cx"> }
</span><ins>+
+ // bit field extract
+ appendInstructionName(extractOpNames());
</ins><span class="cx">
</span><del>- appendInstructionName(opName());
</del><span class="cx"> appendRegisterName(rd(), is64Bit());
</span><span class="cx"> appendSeparator();
</span><span class="cx"> appendRegisterName(rn(), is64Bit());
</span><span class="lines">@@ -380,7 +387,7 @@
</span><span class="cx"> appendSeparator();
</span><span class="cx"> appendUnsignedImmediate(immediateR());
</span><span class="cx"> appendSeparator();
</span><del>- appendUnsignedImmediate(immediateS());
</del><ins>+ appendUnsignedImmediate(immediateS() - immediateR() + 1);
</ins><span class="cx">
</span><span class="cx"> return m_formatBuffer;
</span><span class="cx"> }
</span><span class="lines">@@ -442,6 +449,38 @@
</span><span class="cx">
</span><span class="cx"> }
</span><span class="cx">
</span><ins>+const char* const A64DOpcodeDataProcessing1Source::s_opNames[8] = {
+ "rbit", "rev16", "rev32", "rev", "clz", "cls", 0, 0
+};
+
+const char* A64DOpcodeDataProcessing1Source::format()
+{
+ if (sBit())
+ return A64DOpcode::format();
+
+ if (opCode2())
+ return A64DOpcode::format();
+
+ if (opCode() & 0x38)
+ return A64DOpcode::format();
+
+ if ((opCode() & 0x3e) == 0x6)
+ return A64DOpcode::format();
+
+ if (is64Bit() && opCode() == 0x3)
+ return A64DOpcode::format();
+
+ if (!is64Bit() && opCode() == 0x2)
+ appendInstructionName("rev");
+ else
+ appendInstructionName(opName());
+ appendZROrRegisterName(rd(), is64Bit());
+ appendSeparator();
+ appendZROrRegisterName(rn(), is64Bit());
+
+ return m_formatBuffer;
+}
+
</ins><span class="cx"> const char* const A64DOpcodeDataProcessing2Source::s_opNames[8] = {
</span><span class="cx"> 0, 0, "udiv", "sdiv", "lsl", "lsr", "asr", "ror" // We use the pseudo-op names for the shift/rotate instructions
</span><span class="cx"> };
</span><span class="lines">@@ -461,11 +500,11 @@
</span><span class="cx"> return A64DOpcode::format();
</span><span class="cx">
</span><span class="cx"> appendInstructionName(opName());
</span><del>- appendRegisterName(rd(), is64Bit());
</del><ins>+ appendZROrRegisterName(rd(), is64Bit());
</ins><span class="cx"> appendSeparator();
</span><del>- appendRegisterName(rn(), is64Bit());
</del><ins>+ appendZROrRegisterName(rn(), is64Bit());
</ins><span class="cx"> appendSeparator();
</span><del>- appendRegisterName(rm(), is64Bit());
</del><ins>+ appendZROrRegisterName(rm(), is64Bit());
</ins><span class="cx">
</span><span class="cx"> return m_formatBuffer;
</span><span class="cx"> }
</span><span class="lines">@@ -494,15 +533,18 @@
</span><span class="cx"> if (!opName())
</span><span class="cx"> return A64DOpcode::format();
</span><span class="cx">
</span><ins>+ if ((opNum() & 0x4) && (ra() != 31))
+ return A64DOpcode::format();
+
</ins><span class="cx"> appendInstructionName(opName());
</span><del>- appendRegisterName(rd(), is64Bit());
</del><ins>+ appendZROrRegisterName(rd(), is64Bit());
</ins><span class="cx"> appendSeparator();
</span><span class="cx"> bool srcOneAndTwoAre64Bit = is64Bit() & !(opNum() & 0x2);
</span><del>- appendRegisterName(rn(), srcOneAndTwoAre64Bit);
</del><ins>+ appendZROrRegisterName(rn(), srcOneAndTwoAre64Bit);
</ins><span class="cx"> appendSeparator();
</span><del>- appendRegisterName(rm(), srcOneAndTwoAre64Bit);
</del><ins>+ appendZROrRegisterName(rm(), srcOneAndTwoAre64Bit);
</ins><span class="cx">
</span><del>- if ((ra() != 31) || !(opNum() & 0x4)) {
</del><ins>+ if (ra() != 31) {
</ins><span class="cx"> appendSeparator();
</span><span class="cx"> appendRegisterName(ra(), is64Bit());
</span><span class="cx"> }
</span><span class="lines">@@ -562,24 +604,27 @@
</span><span class="cx">
</span><span class="cx"> const char* A64DOpcodeExtract::format()
</span><span class="cx"> {
</span><del>- if (!op21() || !o0Bit())
</del><ins>+ if (op21() || o0Bit())
</ins><span class="cx"> return A64DOpcode::format();
</span><span class="cx">
</span><span class="cx"> if (is64Bit() != nBit())
</span><span class="cx"> return A64DOpcode::format();
</span><span class="cx">
</span><del>- if (is64Bit() && (immediateS() & 0x20))
</del><ins>+ if (!is64Bit() && (immediateS() & 0x20))
</ins><span class="cx"> return A64DOpcode::format();
</span><span class="cx">
</span><del>- const char* opName = (rn() == rm()) ? "ror" : "extr";
</del><ins>+ bool isROR = rn() == rm();
+ const char* opName = (isROR) ? "ror" : "extr";
</ins><span class="cx">
</span><span class="cx"> appendInstructionName(opName);
</span><del>- appendRegisterName(rd(), is64Bit());
</del><ins>+ appendZROrRegisterName(rd(), is64Bit());
</ins><span class="cx"> appendSeparator();
</span><del>- appendRegisterName(rn(), is64Bit());
</del><ins>+ appendZROrRegisterName(rn(), is64Bit());
+ if (!isROR) {
+ appendSeparator();
+ appendZROrRegisterName(rm(), is64Bit());
+ }
</ins><span class="cx"> appendSeparator();
</span><del>- appendRegisterName(rm(), is64Bit());
- appendSeparator();
</del><span class="cx"> appendUnsignedImmediate(immediateS());
</span><span class="cx">
</span><span class="cx"> return m_formatBuffer;
</span><span class="lines">@@ -614,6 +659,30 @@
</span><span class="cx"> return m_formatBuffer;
</span><span class="cx"> }
</span><span class="cx">
</span><ins>+const char* A64DOpcodeFloatingPointConditionalSelect::format()
+{
+ if (mBit())
+ return A64DOpcode::format();
+
+ if (sBit())
+ return A64DOpcode::format();
+
+ if (type() & 0x2)
+ return A64DOpcode::format();
+
+ appendInstructionName(opName());
+ unsigned registerSize = type() + 2;
+ appendFPRegisterName(rd(), registerSize);
+ appendSeparator();
+ appendFPRegisterName(rn(), registerSize);
+ appendSeparator();
+ appendFPRegisterName(rm(), registerSize);
+ appendSeparator();
+ appendString(conditionName(condition()));
+
+ return m_formatBuffer;
+}
+
</ins><span class="cx"> const char* const A64DOpcodeFloatingPointDataProcessing1Source::s_opNames[16] = {
</span><span class="cx"> "fmov", "fabs", "fneg", "fsqrt", "fcvt", "fcvt", 0, "fcvt",
</span><span class="cx"> "frintn", "frintp", "frintm", "frintz", "frinta", 0, "frintx", "frinti"
</span><span class="lines">@@ -782,10 +851,10 @@
</span><span class="cx"> // fmov Vd.D[1], Xn
</span><span class="cx"> bufferPrintf("V%u.D[1]", rd());
</span><span class="cx"> appendSeparator();
</span><del>- appendRegisterName(rn());
</del><ins>+ appendZROrRegisterName(rn());
</ins><span class="cx"> } else {
</span><span class="cx"> // fmov Xd, Vn.D[1]
</span><del>- appendRegisterName(rd());
</del><ins>+ appendZROrRegisterName(rd());
</ins><span class="cx"> appendSeparator();
</span><span class="cx"> bufferPrintf("V%u.D[1]", rn());
</span><span class="cx"> }
</span><span class="lines">@@ -800,9 +869,9 @@
</span><span class="cx"> if (destIsFP) {
</span><span class="cx"> appendFPRegisterName(rd(), FPRegisterSize);
</span><span class="cx"> appendSeparator();
</span><del>- appendRegisterName(rn(), is64Bit());
</del><ins>+ appendZROrRegisterName(rn(), is64Bit());
</ins><span class="cx"> } else {
</span><del>- appendRegisterName(rd(), is64Bit());
</del><ins>+ appendZROrRegisterName(rd(), is64Bit());
</ins><span class="cx"> appendSeparator();
</span><span class="cx"> appendFPRegisterName(rn(), FPRegisterSize);
</span><span class="cx"> }
</span><span class="lines">@@ -824,17 +893,20 @@
</span><span class="cx"> return m_formatBuffer;
</span><span class="cx"> }
</span><span class="cx">
</span><del>-const char* A64DOpcodeDmbIsh::format()
</del><ins>+const char* const A64DOpcodeDmb::s_optionNames[16] = {
+ 0, "oshld", "oshst", "osh", 0, "nshld", "nshst", "nsh",
+ 0, "ishld", "ishst", "ish", 0, "ld", "st", "sy"
+};
+
+const char* A64DOpcodeDmb::format()
</ins><span class="cx"> {
</span><del>- appendInstructionName("dmb");
- appendString("ish");
- return m_formatBuffer;
-}
</del><ins>+ appendInstructionName(opName());
+ const char* thisOption = option();
+ if (thisOption)
+ appendString(thisOption);
+ else
+ appendUnsignedImmediate(crM());
</ins><span class="cx">
</span><del>-const char* A64DOpcodeDmbIshSt::format()
-{
- appendInstructionName("dmb");
- appendString("ishst");
</del><span class="cx"> return m_formatBuffer;
</span><span class="cx"> }
</span><span class="cx">
</span><span class="lines">@@ -879,6 +951,8 @@
</span><span class="cx"> appendInstructionName(thisOpName);
</span><span class="cx"> if (vBit())
</span><span class="cx"> appendFPRegisterName(rt(), size());
</span><ins>+ else if (!opc())
+ appendZROrRegisterName(rt(), is64BitRT());
</ins><span class="cx"> else
</span><span class="cx"> appendRegisterName(rt(), is64BitRT());
</span><span class="cx"> appendSeparator();
</span><span class="lines">@@ -936,28 +1010,33 @@
</span><span class="cx"> appendFPRegisterName(rt(), size());
</span><span class="cx"> scale = ((opc() & 2)<<1) | size();
</span><span class="cx"> } else {
</span><del>- appendRegisterName(rt(), is64BitRT());
</del><ins>+ if (!opc())
+ appendZROrRegisterName(rt(), is64BitRT());
+ else
+ appendRegisterName(rt(), is64BitRT());
</ins><span class="cx"> scale = size();
</span><span class="cx"> }
</span><span class="cx"> appendSeparator();
</span><span class="cx"> appendCharacter('[');
</span><span class="cx"> appendSPOrRegisterName(rn());
</span><del>- appendSeparator();
- appendZROrRegisterName(rm(), (option() & 0x3) == 0x3);
</del><ins>+ if (rm() != 31) {
+ appendSeparator();
+ appendRegisterName(rm(), (option() & 0x3) == 0x3);
</ins><span class="cx">
</span><del>- unsigned shift = sBit() ? scale : 0;
</del><ins>+ unsigned shift = sBit() ? scale : 0;
</ins><span class="cx">
</span><del>- if (option() == 0x3) {
- if (shift) {
</del><ins>+ if (option() == 0x3) {
+ if (shift) {
+ appendSeparator();
+ appendString("lsl ");
+ appendUnsignedImmediate(shift);
+ }
+ } else {
</ins><span class="cx"> appendSeparator();
</span><del>- appendString("lsl ");
- appendUnsignedImmediate(shift);
</del><ins>+ appendString(optionName());
+ if (shift)
+ appendUnsignedImmediate(shift);
</ins><span class="cx"> }
</span><del>- } else {
- appendSeparator();
- appendString(optionName());
- if (shift)
- appendUnsignedImmediate(shift);
</del><span class="cx"> }
</span><span class="cx">
</span><span class="cx"> appendCharacter(']');
</span><span class="lines">@@ -995,9 +1074,15 @@
</span><span class="cx"> appendFPRegisterName(rt2(), size());
</span><span class="cx"> offsetShift = size() + 2;
</span><span class="cx"> } else {
</span><del>- appendRegisterName(rt(), is64Bit());
</del><ins>+ if (!lBit())
+ appendZROrRegisterName(rt(), is64Bit());
+ else
+ appendRegisterName(rt(), is64Bit());
</ins><span class="cx"> appendSeparator();
</span><del>- appendRegisterName(rt2(), is64Bit());
</del><ins>+ if (!lBit())
+ appendZROrRegisterName(rt2(), is64Bit());
+ else
+ appendRegisterName(rt2(), is64Bit());
</ins><span class="cx"> offsetShift = (size() >> 1) + 2;
</span><span class="cx"> }
</span><span class="cx">
</span><span class="lines">@@ -1035,7 +1120,10 @@
</span><span class="cx"> appendFPRegisterName(rt(), size());
</span><span class="cx"> scale = ((opc() & 2)<<1) | size();
</span><span class="cx"> } else {
</span><del>- appendRegisterName(rt(), is64BitRT());
</del><ins>+ if (!opc())
+ appendZROrRegisterName(rt(), is64BitRT());
+ else
+ appendRegisterName(rt(), is64BitRT());
</ins><span class="cx"> scale = size();
</span><span class="cx"> }
</span><span class="cx"> appendSeparator();
</span><span class="lines">@@ -1066,15 +1154,15 @@
</span><span class="cx"> appendInstructionName("tst");
</span><span class="cx"> else {
</span><span class="cx"> if (isMov())
</span><del>- appendInstructionName("mov");
</del><ins>+ appendInstructionName(nBit() ? "mvn" : "mov");
</ins><span class="cx"> else
</span><span class="cx"> appendInstructionName(opName(opNumber()));
</span><del>- appendSPOrRegisterName(rd(), is64Bit());
</del><ins>+ appendZROrRegisterName(rd(), is64Bit());
</ins><span class="cx"> appendSeparator();
</span><span class="cx"> }
</span><span class="cx">
</span><span class="cx"> if (!isMov()) {
</span><del>- appendRegisterName(rn(), is64Bit());
</del><ins>+ appendZROrRegisterName(rn(), is64Bit());
</ins><span class="cx"> appendSeparator();
</span><span class="cx"> }
</span><span class="cx">
</span><span class="lines">@@ -1158,22 +1246,39 @@
</span><span class="cx"> return m_formatBuffer;
</span><span class="cx"> }
</span><span class="cx">
</span><del>-const char* const A64DOpcodeMoveWide::s_opNames[4] = { "movn", "", "movz", "movk" };
</del><ins>+const char* const A64DOpcodeMoveWide::s_opNames[4] = { "movn", 0, "movz", "movk" };
</ins><span class="cx">
</span><span class="cx"> const char* A64DOpcodeMoveWide::format()
</span><span class="cx"> {
</span><span class="cx"> if (opc() == 1)
</span><span class="cx"> return A64DOpcode::format();
</span><del>- if (!size() && hw() >= 2)
</del><ins>+ if (!is64Bit() && hw() >= 2)
</ins><span class="cx"> return A64DOpcode::format();
</span><span class="cx">
</span><del>- appendInstructionName(opName());
- appendRegisterName(rd(), is64Bit());
- appendSeparator();
- appendUnsignedImmediate(immediate16());
- if (hw()) {
</del><ins>+ if (!opc() && (!immediate16() || !hw()) && (is64Bit() || immediate16() != 0xffff)) {
+ // MOV pseudo op for MOVN
+ appendInstructionName("mov");
+ appendRegisterName(rd(), is64Bit());
</ins><span class="cx"> appendSeparator();
</span><del>- appendShiftAmount(hw());
</del><ins>+
+ if (is64Bit()) {
+ int64_t amount = immediate16() << (hw() * 16);
+ amount = ~amount;
+ appendSignedImmediate64(amount);
+ } else {
+ int32_t amount = immediate16() << (hw() * 16);
+ amount = ~amount;
+ appendSignedImmediate(amount);
+ }
+ } else {
+ appendInstructionName(opName());
+ appendRegisterName(rd(), is64Bit());
+ appendSeparator();
+ appendUnsignedHexImmediate(immediate16());
+ if (hw()) {
+ appendSeparator();
+ appendShiftAmount(hw());
+ }
</ins><span class="cx"> }
</span><span class="cx">
</span><span class="cx"> return m_formatBuffer;
</span></span></pre></div>
<a id="trunkSourceJavaScriptCoredisassemblerARM64A64DOpcodeh"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/disassembler/ARM64/A64DOpcode.h (212591 => 212592)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/disassembler/ARM64/A64DOpcode.h 2017-02-17 23:49:59 UTC (rev 212591)
+++ trunk/Source/JavaScriptCore/disassembler/ARM64/A64DOpcode.h 2017-02-17 23:52:17 UTC (rev 212592)
</span><span class="lines">@@ -164,11 +164,21 @@
</span><span class="cx"> bufferPrintf("#%d", immediate);
</span><span class="cx"> }
</span><span class="cx">
</span><ins>+ void appendSignedImmediate64(int64_t immediate)
+ {
+ bufferPrintf("#%" PRIi64, immediate);
+ }
+
</ins><span class="cx"> void appendUnsignedImmediate(unsigned immediate)
</span><span class="cx"> {
</span><span class="cx"> bufferPrintf("#%u", immediate);
</span><span class="cx"> }
</span><span class="cx">
</span><ins>+ void appendUnsignedHexImmediate(unsigned immediate)
+ {
+ bufferPrintf("#0x%x", immediate);
+ }
+
</ins><span class="cx"> void appendUnsignedImmediate64(uint64_t immediate)
</span><span class="cx"> {
</span><span class="cx"> bufferPrintf("#0x%" PRIx64, immediate);
</span><span class="lines">@@ -312,7 +322,7 @@
</span><span class="cx"> static const char* const s_opNames[4];
</span><span class="cx">
</span><span class="cx"> public:
</span><del>- static const uint32_t mask = 0x1fe00010;
</del><ins>+ static const uint32_t mask = 0x1fe00000;
</ins><span class="cx"> static const uint32_t pattern = 0x1a800000;
</span><span class="cx">
</span><span class="cx"> DEFINE_STATIC_FORMAT(A64DOpcodeConditionalSelect, thisObj);
</span><span class="lines">@@ -327,6 +337,25 @@
</span><span class="cx"> unsigned op2() { return (m_opcode >> 10) & 0x3; }
</span><span class="cx"> };
</span><span class="cx">
</span><ins>+class A64DOpcodeDataProcessing1Source : public A64DOpcode {
+private:
+ static const char* const s_opNames[8];
+
+public:
+ static const uint32_t mask = 0x5fe00000;
+ static const uint32_t pattern = 0x5ac00000;
+
+ DEFINE_STATIC_FORMAT(A64DOpcodeDataProcessing1Source, thisObj);
+
+ const char* format();
+
+ const char* opName() { return s_opNames[opNameIndex()]; }
+ unsigned sBit() { return (m_opcode >> 29) & 0x1; }
+ unsigned opCode() { return (m_opcode >> 10) & 0x3f; }
+ unsigned opCode2() { return (m_opcode >> 16) & 0x1f; }
+ unsigned opNameIndex() { return (opCode() & 0x7); }
+};
+
</ins><span class="cx"> class A64DOpcodeDataProcessing2Source : public A64DOpcode {
</span><span class="cx"> private:
</span><span class="cx"> static const char* const s_opNames[8];
</span><span class="lines">@@ -358,7 +387,7 @@
</span><span class="cx">
</span><span class="cx"> const char* format();
</span><span class="cx">
</span><del>- const char* opName() { return ra() == 31 ? s_opNames[opNum() & 0xf] : s_pseudoOpNames[opNum() & 0xf]; }
</del><ins>+ const char* opName() { return ra() == 31 ? s_pseudoOpNames[opNum() & 0xf] : s_opNames[opNum() & 0xf]; }
</ins><span class="cx"> unsigned ra() { return (m_opcode >> 10) & 0x1f; }
</span><span class="cx"> unsigned op54() { return (m_opcode >> 29) & 0x3; }
</span><span class="cx"> unsigned op31() { return (m_opcode >> 21) & 0x7; }
</span><span class="lines">@@ -368,7 +397,7 @@
</span><span class="cx">
</span><span class="cx"> class A64OpcodeExceptionGeneration : public A64DOpcode {
</span><span class="cx"> public:
</span><del>- static const uint32_t mask = 0xff000010;
</del><ins>+ static const uint32_t mask = 0xff000000;
</ins><span class="cx"> static const uint32_t pattern = 0xd4000000;
</span><span class="cx">
</span><span class="cx"> DEFINE_STATIC_FORMAT(A64OpcodeExceptionGeneration, thisObj);
</span><span class="lines">@@ -422,6 +451,20 @@
</span><span class="cx"> unsigned opNum() { return (m_opcode >> 3) & 0x3; }
</span><span class="cx"> };
</span><span class="cx">
</span><ins>+class A64DOpcodeFloatingPointConditionalSelect : public A64DOpcodeFloatingPointOps {
+public:
+ static const uint32_t mask = 0x5f200c00;
+ static const uint32_t pattern = 0x1e200c00;
+
+ DEFINE_STATIC_FORMAT(A64DOpcodeFloatingPointConditionalSelect, thisObj);
+
+ const char* format();
+
+ const char* opName() { return "fcsel"; }
+
+ unsigned condition() { return (m_opcode >> 12) & 0xf; }
+};
+
</ins><span class="cx"> class A64DOpcodeFloatingPointDataProcessing1Source : public A64DOpcodeFloatingPointOps {
</span><span class="cx"> private:
</span><span class="cx"> static const char* const s_opNames[16];
</span><span class="lines">@@ -509,28 +552,20 @@
</span><span class="cx"> unsigned immediate7() { return (m_opcode >> 5) & 0x7f; }
</span><span class="cx"> };
</span><span class="cx">
</span><del>-class A64DOpcodeDmbIsh : public A64DOpcode {
-public:
- static const uint32_t mask = 0xffffffff;
- static const uint32_t pattern = 0xd5033bbf;
</del><ins>+class A64DOpcodeDmb : public A64DOpcode {
+ static const char* const s_optionNames[16];
</ins><span class="cx">
</span><del>- DEFINE_STATIC_FORMAT(A64DOpcodeDmbIsh, thisObj);
-
- const char* format();
-
- const char* opName() { return "dmb"; }
-};
-
-class A64DOpcodeDmbIshSt : public A64DOpcode {
</del><span class="cx"> public:
</span><del>- static const uint32_t mask = 0xffffffff;
- static const uint32_t pattern = 0xd5033abf;
</del><ins>+ static const uint32_t mask = 0xfffff0ff;
+ static const uint32_t pattern = 0xd50330bf;
</ins><span class="cx">
</span><del>- DEFINE_STATIC_FORMAT(A64DOpcodeDmbIshSt, thisObj);
</del><ins>+ DEFINE_STATIC_FORMAT(A64DOpcodeDmb, thisObj);
</ins><span class="cx">
</span><span class="cx"> const char* format();
</span><span class="cx">
</span><span class="cx"> const char* opName() { return "dmb"; }
</span><ins>+ const char* option() { return s_optionNames[crM()]; }
+ unsigned crM() { return (m_opcode >> 8) & 0xf; }
</ins><span class="cx"> };
</span><span class="cx">
</span><span class="cx"> class A64DOpcodeLoadStore : public A64DOpcode {
</span><span class="lines">@@ -657,7 +692,7 @@
</span><span class="cx"> const char* format();
</span><span class="cx">
</span><span class="cx"> bool isTst() { return ((opNumber() == 6) && (rd() == 31)); }
</span><del>- bool isMov() { return ((opNumber() == 2) && (rn() == 31)); }
</del><ins>+ bool isMov() { return ((opc() == 1) && (rn() == 31)); }
</ins><span class="cx"> unsigned opNumber() { return (opc() << 1) | nBit(); }
</span><span class="cx"> unsigned shift() { return (m_opcode >> 22) & 0x3; }
</span><span class="cx"> int immediate6() { return (static_cast<int>((m_opcode >> 10) & 0x3f) << 26) >> 26; }
</span></span></pre>
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