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<title>[198905] trunk/Source/JavaScriptCore</title>
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<dl class="meta">
<dt>Revision</dt> <dd><a href="http://trac.webkit.org/projects/webkit/changeset/198905">198905</a></dd>
<dt>Author</dt> <dd>benjamin@webkit.org</dd>
<dt>Date</dt> <dd>2016-03-31 11:54:36 -0700 (Thu, 31 Mar 2016)</dd>
</dl>
<h3>Log Message</h3>
<pre>[JSC][x86] Add the indexed forms of floating point addition and multiplication
https://bugs.webkit.org/show_bug.cgi?id=156058
Reviewed by Geoffrey Garen.
B3 supports lowering [base, index] addresses into
arbitrary instructions but we were not using that feature.
This patch adds the missing support for the lowering
of Add and Mul.
* assembler/MacroAssemblerX86Common.h:
(JSC::MacroAssemblerX86Common::addDouble):
(JSC::MacroAssemblerX86Common::addFloat):
(JSC::MacroAssemblerX86Common::mulDouble):
(JSC::MacroAssemblerX86Common::mulFloat):
* assembler/X86Assembler.h:
(JSC::X86Assembler::addsd_mr):
(JSC::X86Assembler::vaddsd_mr):
(JSC::X86Assembler::addss_mr):
(JSC::X86Assembler::vaddss_mr):
(JSC::X86Assembler::mulsd_mr):
(JSC::X86Assembler::vmulsd_mr):
(JSC::X86Assembler::mulss_mr):
(JSC::X86Assembler::vmulss_mr):
(JSC::X86Assembler::X86InstructionFormatter::SingleInstructionBufferWriter::memoryModRM):
* b3/B3LowerToAir.cpp:
(JSC::B3::Air::LowerToAir::appendBinOp):
Unlike the Addr form, we never need to transform a Tmp
into an Index for spilling.
Instead of duplicating all the code in MacroAssembler, I can
just have the lowering phase try using addresses for the first
argument when possible.
* b3/air/AirOpcode.opcodes:
* b3/air/testair.cpp:
(JSC::B3::Air::testX86VMULSDBaseNeedsRex):
(JSC::B3::Air::testX86VMULSDIndexNeedsRex):
(JSC::B3::Air::testX86VMULSDBaseIndexNeedRex):
(JSC::B3::Air::run):</pre>
<h3>Modified Paths</h3>
<ul>
<li><a href="#trunkSourceJavaScriptCoreChangeLog">trunk/Source/JavaScriptCore/ChangeLog</a></li>
<li><a href="#trunkSourceJavaScriptCoreassemblerMacroAssemblerX86Commonh">trunk/Source/JavaScriptCore/assembler/MacroAssemblerX86Common.h</a></li>
<li><a href="#trunkSourceJavaScriptCoreassemblerX86Assemblerh">trunk/Source/JavaScriptCore/assembler/X86Assembler.h</a></li>
<li><a href="#trunkSourceJavaScriptCoreb3B3LowerToAircpp">trunk/Source/JavaScriptCore/b3/B3LowerToAir.cpp</a></li>
<li><a href="#trunkSourceJavaScriptCoreb3airAirOpcodeopcodes">trunk/Source/JavaScriptCore/b3/air/AirOpcode.opcodes</a></li>
<li><a href="#trunkSourceJavaScriptCoreb3airtestaircpp">trunk/Source/JavaScriptCore/b3/air/testair.cpp</a></li>
</ul>
</div>
<div id="patch">
<h3>Diff</h3>
<a id="trunkSourceJavaScriptCoreChangeLog"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/ChangeLog (198904 => 198905)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/ChangeLog 2016-03-31 18:50:55 UTC (rev 198904)
+++ trunk/Source/JavaScriptCore/ChangeLog 2016-03-31 18:54:36 UTC (rev 198905)
</span><span class="lines">@@ -1,3 +1,47 @@
</span><ins>+2016-03-31 Benjamin Poulain <benjamin@webkit.org>
+
+ [JSC][x86] Add the indexed forms of floating point addition and multiplication
+ https://bugs.webkit.org/show_bug.cgi?id=156058
+
+ Reviewed by Geoffrey Garen.
+
+ B3 supports lowering [base, index] addresses into
+ arbitrary instructions but we were not using that feature.
+
+ This patch adds the missing support for the lowering
+ of Add and Mul.
+
+ * assembler/MacroAssemblerX86Common.h:
+ (JSC::MacroAssemblerX86Common::addDouble):
+ (JSC::MacroAssemblerX86Common::addFloat):
+ (JSC::MacroAssemblerX86Common::mulDouble):
+ (JSC::MacroAssemblerX86Common::mulFloat):
+ * assembler/X86Assembler.h:
+ (JSC::X86Assembler::addsd_mr):
+ (JSC::X86Assembler::vaddsd_mr):
+ (JSC::X86Assembler::addss_mr):
+ (JSC::X86Assembler::vaddss_mr):
+ (JSC::X86Assembler::mulsd_mr):
+ (JSC::X86Assembler::vmulsd_mr):
+ (JSC::X86Assembler::mulss_mr):
+ (JSC::X86Assembler::vmulss_mr):
+ (JSC::X86Assembler::X86InstructionFormatter::SingleInstructionBufferWriter::memoryModRM):
+ * b3/B3LowerToAir.cpp:
+ (JSC::B3::Air::LowerToAir::appendBinOp):
+ Unlike the Addr form, we never need to transform a Tmp
+ into an Index for spilling.
+
+ Instead of duplicating all the code in MacroAssembler, I can
+ just have the lowering phase try using addresses for the first
+ argument when possible.
+
+ * b3/air/AirOpcode.opcodes:
+ * b3/air/testair.cpp:
+ (JSC::B3::Air::testX86VMULSDBaseNeedsRex):
+ (JSC::B3::Air::testX86VMULSDIndexNeedsRex):
+ (JSC::B3::Air::testX86VMULSDBaseIndexNeedRex):
+ (JSC::B3::Air::run):
+
</ins><span class="cx"> 2016-03-31 Saam barati <sbarati@apple.com>
</span><span class="cx">
</span><span class="cx"> DFG JIT bug in typeof constant folding where the input to typeof is an object or function
</span></span></pre></div>
<a id="trunkSourceJavaScriptCoreassemblerMacroAssemblerX86Commonh"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/assembler/MacroAssemblerX86Common.h (198904 => 198905)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/assembler/MacroAssemblerX86Common.h 2016-03-31 18:50:55 UTC (rev 198904)
+++ trunk/Source/JavaScriptCore/assembler/MacroAssemblerX86Common.h 2016-03-31 18:54:36 UTC (rev 198905)
</span><span class="lines">@@ -1134,6 +1134,21 @@
</span><span class="cx"> addDouble(op2, op1, dest);
</span><span class="cx"> }
</span><span class="cx">
</span><ins>+ void addDouble(BaseIndex op1, FPRegisterID op2, FPRegisterID dest)
+ {
+ if (supportsAVX())
+ m_assembler.vaddsd_mr(op1.offset, op1.base, op1.index, op1.scale, op2, dest);
+ else {
+ ASSERT(isSSE2Present());
+ if (op2 == dest) {
+ m_assembler.addsd_mr(op1.offset, op1.base, op1.index, op1.scale, dest);
+ return;
+ }
+ loadDouble(op1, dest);
+ addDouble(op2, dest);
+ }
+ }
+
</ins><span class="cx"> void addFloat(FPRegisterID src, FPRegisterID dest)
</span><span class="cx"> {
</span><span class="cx"> addFloat(src, dest, dest);
</span><span class="lines">@@ -1180,6 +1195,21 @@
</span><span class="cx"> addFloat(op2, op1, dest);
</span><span class="cx"> }
</span><span class="cx">
</span><ins>+ void addFloat(BaseIndex op1, FPRegisterID op2, FPRegisterID dest)
+ {
+ if (supportsAVX())
+ m_assembler.vaddss_mr(op1.offset, op1.base, op1.index, op1.scale, op2, dest);
+ else {
+ ASSERT(isSSE2Present());
+ if (op2 == dest) {
+ m_assembler.addss_mr(op1.offset, op1.base, op1.index, op1.scale, dest);
+ return;
+ }
+ loadFloat(op1, dest);
+ addFloat(op2, dest);
+ }
+ }
+
</ins><span class="cx"> void divDouble(FPRegisterID src, FPRegisterID dest)
</span><span class="cx"> {
</span><span class="cx"> ASSERT(isSSE2Present());
</span><span class="lines">@@ -1291,6 +1321,21 @@
</span><span class="cx"> return mulDouble(op2, op1, dest);
</span><span class="cx"> }
</span><span class="cx">
</span><ins>+ void mulDouble(BaseIndex op1, FPRegisterID op2, FPRegisterID dest)
+ {
+ if (supportsAVX())
+ m_assembler.vmulsd_mr(op1.offset, op1.base, op1.index, op1.scale, op2, dest);
+ else {
+ ASSERT(isSSE2Present());
+ if (op2 == dest) {
+ m_assembler.mulsd_mr(op1.offset, op1.base, op1.index, op1.scale, dest);
+ return;
+ }
+ loadDouble(op1, dest);
+ mulDouble(op2, dest);
+ }
+ }
+
</ins><span class="cx"> void mulFloat(FPRegisterID src, FPRegisterID dest)
</span><span class="cx"> {
</span><span class="cx"> mulFloat(src, dest, dest);
</span><span class="lines">@@ -1336,6 +1381,21 @@
</span><span class="cx"> mulFloat(op2, op1, dest);
</span><span class="cx"> }
</span><span class="cx">
</span><ins>+ void mulFloat(BaseIndex op1, FPRegisterID op2, FPRegisterID dest)
+ {
+ if (supportsAVX())
+ m_assembler.vmulss_mr(op1.offset, op1.base, op1.index, op1.scale, op2, dest);
+ else {
+ ASSERT(isSSE2Present());
+ if (op2 == dest) {
+ m_assembler.mulss_mr(op1.offset, op1.base, op1.index, op1.scale, dest);
+ return;
+ }
+ loadFloat(op1, dest);
+ mulFloat(op2, dest);
+ }
+ }
+
</ins><span class="cx"> void andDouble(FPRegisterID src, FPRegisterID dst)
</span><span class="cx"> {
</span><span class="cx"> // ANDPS is defined on 128bits and is shorter than ANDPD.
</span></span></pre></div>
<a id="trunkSourceJavaScriptCoreassemblerX86Assemblerh"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/assembler/X86Assembler.h (198904 => 198905)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/assembler/X86Assembler.h 2016-03-31 18:50:55 UTC (rev 198904)
+++ trunk/Source/JavaScriptCore/assembler/X86Assembler.h 2016-03-31 18:54:36 UTC (rev 198905)
</span><span class="lines">@@ -2109,11 +2109,22 @@
</span><span class="cx"> m_formatter.twoByteOp(OP2_ADDSD_VsdWsd, (RegisterID)dst, base, offset);
</span><span class="cx"> }
</span><span class="cx">
</span><ins>+ void addsd_mr(int offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst)
+ {
+ m_formatter.prefix(PRE_SSE_F2);
+ m_formatter.twoByteOp(OP2_ADDSD_VsdWsd, dst, base, index, scale, offset);
+ }
+
</ins><span class="cx"> void vaddsd_mr(int offset, RegisterID base, XMMRegisterID b, XMMRegisterID dst)
</span><span class="cx"> {
</span><span class="cx"> m_formatter.vexNdsLigWigTwoByteOp(PRE_SSE_F2, OP2_ADDSD_VsdWsd, (RegisterID)dst, (RegisterID)b, base, offset);
</span><span class="cx"> }
</span><span class="cx">
</span><ins>+ void vaddsd_mr(int offset, RegisterID base, RegisterID index, int scale, XMMRegisterID b, XMMRegisterID dst)
+ {
+ m_formatter.vexNdsLigWigTwoByteOp(PRE_SSE_F2, OP2_ADDSD_VsdWsd, (RegisterID)dst, (RegisterID)b, offset, base, index, scale);
+ }
+
</ins><span class="cx"> void addss_rr(XMMRegisterID src, XMMRegisterID dst)
</span><span class="cx"> {
</span><span class="cx"> m_formatter.prefix(PRE_SSE_F3);
</span><span class="lines">@@ -2131,11 +2142,22 @@
</span><span class="cx"> m_formatter.twoByteOp(OP2_ADDSD_VsdWsd, (RegisterID)dst, base, offset);
</span><span class="cx"> }
</span><span class="cx">
</span><ins>+ void addss_mr(int offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst)
+ {
+ m_formatter.prefix(PRE_SSE_F3);
+ m_formatter.twoByteOp(OP2_ADDSD_VsdWsd, dst, base, index, scale, offset);
+ }
+
</ins><span class="cx"> void vaddss_mr(int offset, RegisterID base, XMMRegisterID b, XMMRegisterID dst)
</span><span class="cx"> {
</span><span class="cx"> m_formatter.vexNdsLigWigTwoByteOp(PRE_SSE_F3, OP2_ADDSD_VsdWsd, (RegisterID)dst, (RegisterID)b, base, offset);
</span><span class="cx"> }
</span><span class="cx">
</span><ins>+ void vaddss_mr(int offset, RegisterID base, RegisterID index, int scale, XMMRegisterID b, XMMRegisterID dst)
+ {
+ m_formatter.vexNdsLigWigTwoByteOp(PRE_SSE_F3, OP2_ADDSD_VsdWsd, (RegisterID)dst, (RegisterID)b, offset, base, index, scale);
+ }
+
</ins><span class="cx"> #if !CPU(X86_64)
</span><span class="cx"> void addsd_mr(const void* address, XMMRegisterID dst)
</span><span class="cx"> {
</span><span class="lines">@@ -2337,11 +2359,22 @@
</span><span class="cx"> m_formatter.twoByteOp(OP2_MULSD_VsdWsd, (RegisterID)dst, base, offset);
</span><span class="cx"> }
</span><span class="cx">
</span><ins>+ void mulsd_mr(int offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst)
+ {
+ m_formatter.prefix(PRE_SSE_F2);
+ m_formatter.twoByteOp(OP2_MULSD_VsdWsd, dst, base, index, scale, offset);
+ }
+
</ins><span class="cx"> void vmulsd_mr(int offset, RegisterID base, XMMRegisterID b, XMMRegisterID dst)
</span><span class="cx"> {
</span><span class="cx"> m_formatter.vexNdsLigWigTwoByteOp(PRE_SSE_F2, OP2_MULSD_VsdWsd, (RegisterID)dst, (RegisterID)b, base, offset);
</span><span class="cx"> }
</span><span class="cx">
</span><ins>+ void vmulsd_mr(int offset, RegisterID base, RegisterID index, int scale, XMMRegisterID b, XMMRegisterID dst)
+ {
+ m_formatter.vexNdsLigWigTwoByteOp(PRE_SSE_F2, OP2_MULSD_VsdWsd, (RegisterID)dst, (RegisterID)b, offset, base, index, scale);
+ }
+
</ins><span class="cx"> void mulss_rr(XMMRegisterID src, XMMRegisterID dst)
</span><span class="cx"> {
</span><span class="cx"> m_formatter.prefix(PRE_SSE_F3);
</span><span class="lines">@@ -2359,11 +2392,22 @@
</span><span class="cx"> m_formatter.twoByteOp(OP2_MULSD_VsdWsd, (RegisterID)dst, base, offset);
</span><span class="cx"> }
</span><span class="cx">
</span><ins>+ void mulss_mr(int offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst)
+ {
+ m_formatter.prefix(PRE_SSE_F3);
+ m_formatter.twoByteOp(OP2_MULSD_VsdWsd, dst, base, index, scale, offset);
+ }
+
</ins><span class="cx"> void vmulss_mr(int offset, RegisterID base, XMMRegisterID b, XMMRegisterID dst)
</span><span class="cx"> {
</span><span class="cx"> m_formatter.vexNdsLigWigTwoByteOp(PRE_SSE_F3, OP2_MULSD_VsdWsd, (RegisterID)dst, (RegisterID)b, base, offset);
</span><span class="cx"> }
</span><span class="cx">
</span><ins>+ void vmulss_mr(int offset, RegisterID base, RegisterID index, int scale, XMMRegisterID b, XMMRegisterID dst)
+ {
+ m_formatter.vexNdsLigWigTwoByteOp(PRE_SSE_F3, OP2_MULSD_VsdWsd, (RegisterID)dst, (RegisterID)b, offset, base, index, scale);
+ }
+
</ins><span class="cx"> void pextrw_irr(int whichWord, XMMRegisterID src, RegisterID dst)
</span><span class="cx"> {
</span><span class="cx"> m_formatter.prefix(PRE_SSE_66);
</span><span class="lines">@@ -3129,6 +3173,21 @@
</span><span class="cx"> putByteUnchecked(secondByte);
</span><span class="cx"> }
</span><span class="cx">
</span><ins>+ ALWAYS_INLINE void threeBytesVexNds(OneByteOpcodeID simdPrefix, VexImpliedBytes impliedBytes, RegisterID r, RegisterID inOpReg, RegisterID x, RegisterID b)
+ {
+ putByteUnchecked(VexPrefix::ThreeBytes);
+
+ uint8_t secondByte = static_cast<uint8_t>(impliedBytes);
+ secondByte |= !regRequiresRex(r) << 7;
+ secondByte |= !regRequiresRex(x) << 6;
+ secondByte |= !regRequiresRex(b) << 5;
+ putByteUnchecked(secondByte);
+
+ uint8_t thirdByte = vexEncodeSimdPrefix(simdPrefix);
+ thirdByte |= (~inOpReg & 0xf) << 3;
+ putByteUnchecked(thirdByte);
+ }
+
</ins><span class="cx"> ALWAYS_INLINE void threeBytesVexNds(OneByteOpcodeID simdPrefix, VexImpliedBytes impliedBytes, RegisterID r, RegisterID inOpReg, RegisterID b)
</span><span class="cx"> {
</span><span class="cx"> putByteUnchecked(VexPrefix::ThreeBytes);
</span><span class="lines">@@ -3307,6 +3366,17 @@
</span><span class="cx"> writer.memoryModRM(dest, base, offset);
</span><span class="cx"> }
</span><span class="cx">
</span><ins>+ void vexNdsLigWigTwoByteOp(OneByteOpcodeID simdPrefix, TwoByteOpcodeID opcode, RegisterID dest, RegisterID a, int offset, RegisterID base, RegisterID index, int scale)
+ {
+ SingleInstructionBufferWriter writer(m_buffer);
+ if (regRequiresRex(base, index))
+ writer.threeBytesVexNds(simdPrefix, VexImpliedBytes::TwoBytesOp, dest, a, index, base);
+ else
+ writer.twoBytesVex(simdPrefix, a, dest);
+ writer.putByteUnchecked(opcode);
+ writer.memoryModRM(dest, base, index, scale, offset);
+ }
+
</ins><span class="cx"> void threeByteOp(TwoByteOpcodeID twoBytePrefix, ThreeByteOpcodeID opcode)
</span><span class="cx"> {
</span><span class="cx"> SingleInstructionBufferWriter writer(m_buffer);
</span></span></pre></div>
<a id="trunkSourceJavaScriptCoreb3B3LowerToAircpp"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/b3/B3LowerToAir.cpp (198904 => 198905)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/b3/B3LowerToAir.cpp 2016-03-31 18:50:55 UTC (rev 198904)
+++ trunk/Source/JavaScriptCore/b3/B3LowerToAir.cpp 2016-03-31 18:54:36 UTC (rev 198905)
</span><span class="lines">@@ -734,6 +734,14 @@
</span><span class="cx"> append(opcode, tmp(left), rightAddr.consume(*this), result);
</span><span class="cx"> return;
</span><span class="cx"> }
</span><ins>+
+ if (commutativity == Commutative) {
+ if (isValidForm(opcode, rightAddr.kind(), Arg::Tmp, Arg::Tmp)) {
+ append(opcode, rightAddr.consume(*this), tmp(left), result);
+ return;
+ }
+ }
+
</ins><span class="cx"> if (isValidForm(opcode, rightAddr.kind(), Arg::Tmp)) {
</span><span class="cx"> append(relaxedMoveForType(m_value->type()), tmp(left), result);
</span><span class="cx"> append(opcode, rightAddr.consume(*this), result);
</span></span></pre></div>
<a id="trunkSourceJavaScriptCoreb3airAirOpcodeopcodes"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/b3/air/AirOpcode.opcodes (198904 => 198905)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/b3/air/AirOpcode.opcodes 2016-03-31 18:50:55 UTC (rev 198904)
+++ trunk/Source/JavaScriptCore/b3/air/AirOpcode.opcodes 2016-03-31 18:54:36 UTC (rev 198905)
</span><span class="lines">@@ -147,6 +147,7 @@
</span><span class="cx"> Tmp, Tmp, Tmp
</span><span class="cx"> x86: Addr, Tmp, Tmp
</span><span class="cx"> x86: Tmp, Addr, Tmp
</span><ins>+ x86: Index, Tmp, Tmp
</ins><span class="cx">
</span><span class="cx"> x86: AddDouble U:F:64, UD:F:64
</span><span class="cx"> Tmp, Tmp
</span><span class="lines">@@ -156,6 +157,7 @@
</span><span class="cx"> Tmp, Tmp, Tmp
</span><span class="cx"> x86: Addr, Tmp, Tmp
</span><span class="cx"> x86: Tmp, Addr, Tmp
</span><ins>+ x86: Index, Tmp, Tmp
</ins><span class="cx">
</span><span class="cx"> x86: AddFloat U:F:32, UD:F:32
</span><span class="cx"> Tmp, Tmp
</span><span class="lines">@@ -243,6 +245,7 @@
</span><span class="cx"> Tmp, Tmp, Tmp
</span><span class="cx"> x86: Addr, Tmp, Tmp
</span><span class="cx"> x86: Tmp, Addr, Tmp
</span><ins>+ x86: Index, Tmp, Tmp
</ins><span class="cx">
</span><span class="cx"> x86: MulDouble U:F:64, UD:F:64
</span><span class="cx"> Tmp, Tmp
</span><span class="lines">@@ -252,6 +255,7 @@
</span><span class="cx"> Tmp, Tmp, Tmp
</span><span class="cx"> x86: Addr, Tmp, Tmp
</span><span class="cx"> x86: Tmp, Addr, Tmp
</span><ins>+ x86: Index, Tmp, Tmp
</ins><span class="cx">
</span><span class="cx"> x86: MulFloat U:F:32, UD:F:32
</span><span class="cx"> Tmp, Tmp
</span></span></pre></div>
<a id="trunkSourceJavaScriptCoreb3airtestaircpp"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/b3/air/testair.cpp (198904 => 198905)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/b3/air/testair.cpp 2016-03-31 18:50:55 UTC (rev 198904)
+++ trunk/Source/JavaScriptCore/b3/air/testair.cpp 2016-03-31 18:54:36 UTC (rev 198905)
</span><span class="lines">@@ -1776,6 +1776,55 @@
</span><span class="cx"> CHECK(compileAndRun<double>(proc, 2.4, &secondArg - 1, pureNaN()) == 2.4 * 4.2);
</span><span class="cx"> }
</span><span class="cx">
</span><ins>+void testX86VMULSDBaseNeedsRex()
+{
+ B3::Procedure proc;
+ Code& code = proc.code();
+
+ BasicBlock* root = code.addBlock();
+ root->append(Move, nullptr, Tmp(GPRInfo::argumentGPR0), Tmp(X86Registers::r13));
+ root->append(MulDouble, nullptr, Arg::index(Tmp(X86Registers::r13), Tmp(GPRInfo::argumentGPR1)), Tmp(FPRInfo::argumentFPR0), Tmp(X86Registers::xmm0));
+ root->append(MoveDouble, nullptr, Tmp(X86Registers::xmm0), Tmp(FPRInfo::returnValueFPR));
+ root->append(RetDouble, nullptr, Tmp(FPRInfo::returnValueFPR));
+
+ double secondArg = 4.2;
+ uint64_t index = 8;
+ CHECK(compileAndRun<double>(proc, 2.4, &secondArg - 1, index, pureNaN()) == 2.4 * 4.2);
+}
+
+void testX86VMULSDIndexNeedsRex()
+{
+ B3::Procedure proc;
+ Code& code = proc.code();
+
+ BasicBlock* root = code.addBlock();
+ root->append(Move, nullptr, Tmp(GPRInfo::argumentGPR1), Tmp(X86Registers::r13));
+ root->append(MulDouble, nullptr, Arg::index(Tmp(GPRInfo::argumentGPR0), Tmp(X86Registers::r13)), Tmp(FPRInfo::argumentFPR0), Tmp(X86Registers::xmm0));
+ root->append(MoveDouble, nullptr, Tmp(X86Registers::xmm0), Tmp(FPRInfo::returnValueFPR));
+ root->append(RetDouble, nullptr, Tmp(FPRInfo::returnValueFPR));
+
+ double secondArg = 4.2;
+ uint64_t index = - 8;
+ CHECK(compileAndRun<double>(proc, 2.4, &secondArg + 1, index, pureNaN()) == 2.4 * 4.2);
+}
+
+void testX86VMULSDBaseIndexNeedRex()
+{
+ B3::Procedure proc;
+ Code& code = proc.code();
+
+ BasicBlock* root = code.addBlock();
+ root->append(Move, nullptr, Tmp(GPRInfo::argumentGPR0), Tmp(X86Registers::r12));
+ root->append(Move, nullptr, Tmp(GPRInfo::argumentGPR1), Tmp(X86Registers::r13));
+ root->append(MulDouble, nullptr, Arg::index(Tmp(X86Registers::r12), Tmp(X86Registers::r13)), Tmp(FPRInfo::argumentFPR0), Tmp(X86Registers::xmm0));
+ root->append(MoveDouble, nullptr, Tmp(X86Registers::xmm0), Tmp(FPRInfo::returnValueFPR));
+ root->append(RetDouble, nullptr, Tmp(FPRInfo::returnValueFPR));
+
+ double secondArg = 4.2;
+ uint64_t index = 16;
+ CHECK(compileAndRun<double>(proc, 2.4, &secondArg - 2, index, pureNaN()) == 2.4 * 4.2);
+}
+
</ins><span class="cx"> #endif
</span><span class="cx">
</span><span class="cx"> #define RUN(test) do { \
</span><span class="lines">@@ -1850,6 +1899,10 @@
</span><span class="cx"> RUN(testX86VMULSDDestRexAddr());
</span><span class="cx"> RUN(testX86VMULSDRegOpDestRexAddr());
</span><span class="cx"> RUN(testX86VMULSDAddrOpDestRexAddr());
</span><ins>+
+ RUN(testX86VMULSDBaseNeedsRex());
+ RUN(testX86VMULSDIndexNeedsRex());
+ RUN(testX86VMULSDBaseIndexNeedRex());
</ins><span class="cx"> #endif
</span><span class="cx">
</span><span class="cx"> if (tasks.isEmpty())
</span></span></pre>
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