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<title>[198832] trunk/Source/JavaScriptCore</title>
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<div id="msg">
<dl class="meta">
<dt>Revision</dt> <dd><a href="http://trac.webkit.org/projects/webkit/changeset/198832">198832</a></dd>
<dt>Author</dt> <dd>benjamin@webkit.org</dd>
<dt>Date</dt> <dd>2016-03-30 00:17:14 -0700 (Wed, 30 Mar 2016)</dd>
</dl>
<h3>Log Message</h3>
<pre>[JSC] Update udis86
https://bugs.webkit.org/show_bug.cgi?id=156005
Reviewed by Geoffrey Garen.
* CMakeLists.txt:
* DerivedSources.make:
* JavaScriptCore.xcodeproj/project.pbxproj:
* disassembler/udis86/differences.txt:
* disassembler/udis86/itab.py: Removed.
* disassembler/udis86/optable.xml:
* disassembler/udis86/ud_itab.py: Added.
* disassembler/udis86/ud_opcode.py:
* disassembler/udis86/ud_optable.py: Removed.
* disassembler/udis86/udis86.c:
* disassembler/udis86/udis86_decode.c:
* disassembler/udis86/udis86_decode.h:
* disassembler/udis86/udis86_extern.h:
* disassembler/udis86/udis86_input.c: Removed.
* disassembler/udis86/udis86_input.h: Removed.
* disassembler/udis86/udis86_syn-att.c:
* disassembler/udis86/udis86_syn.h:
* disassembler/udis86/udis86_types.h:
* disassembler/udis86/udis86_udint.h:</pre>
<h3>Modified Paths</h3>
<ul>
<li><a href="#trunkSourceJavaScriptCoreCMakeListstxt">trunk/Source/JavaScriptCore/CMakeLists.txt</a></li>
<li><a href="#trunkSourceJavaScriptCoreChangeLog">trunk/Source/JavaScriptCore/ChangeLog</a></li>
<li><a href="#trunkSourceJavaScriptCoreDerivedSourcesmake">trunk/Source/JavaScriptCore/DerivedSources.make</a></li>
<li><a href="#trunkSourceJavaScriptCoreJavaScriptCorexcodeprojprojectpbxproj">trunk/Source/JavaScriptCore/JavaScriptCore.xcodeproj/project.pbxproj</a></li>
<li><a href="#trunkSourceJavaScriptCoredisassemblerudis86differencestxt">trunk/Source/JavaScriptCore/disassembler/udis86/differences.txt</a></li>
<li><a href="#trunkSourceJavaScriptCoredisassemblerudis86optablexml">trunk/Source/JavaScriptCore/disassembler/udis86/optable.xml</a></li>
<li><a href="#trunkSourceJavaScriptCoredisassemblerudis86ud_opcodepy">trunk/Source/JavaScriptCore/disassembler/udis86/ud_opcode.py</a></li>
<li><a href="#trunkSourceJavaScriptCoredisassemblerudis86udis86c">trunk/Source/JavaScriptCore/disassembler/udis86/udis86.c</a></li>
<li><a href="#trunkSourceJavaScriptCoredisassemblerudis86udis86_decodec">trunk/Source/JavaScriptCore/disassembler/udis86/udis86_decode.c</a></li>
<li><a href="#trunkSourceJavaScriptCoredisassemblerudis86udis86_decodeh">trunk/Source/JavaScriptCore/disassembler/udis86/udis86_decode.h</a></li>
<li><a href="#trunkSourceJavaScriptCoredisassemblerudis86udis86_externh">trunk/Source/JavaScriptCore/disassembler/udis86/udis86_extern.h</a></li>
<li><a href="#trunkSourceJavaScriptCoredisassemblerudis86udis86_synattc">trunk/Source/JavaScriptCore/disassembler/udis86/udis86_syn-att.c</a></li>
<li><a href="#trunkSourceJavaScriptCoredisassemblerudis86udis86_synintelc">trunk/Source/JavaScriptCore/disassembler/udis86/udis86_syn-intel.c</a></li>
<li><a href="#trunkSourceJavaScriptCoredisassemblerudis86udis86_sync">trunk/Source/JavaScriptCore/disassembler/udis86/udis86_syn.c</a></li>
<li><a href="#trunkSourceJavaScriptCoredisassemblerudis86udis86_synh">trunk/Source/JavaScriptCore/disassembler/udis86/udis86_syn.h</a></li>
<li><a href="#trunkSourceJavaScriptCoredisassemblerudis86udis86_typesh">trunk/Source/JavaScriptCore/disassembler/udis86/udis86_types.h</a></li>
</ul>
<h3>Added Paths</h3>
<ul>
<li><a href="#trunkSourceJavaScriptCoredisassemblerudis86ud_itabpy">trunk/Source/JavaScriptCore/disassembler/udis86/ud_itab.py</a></li>
<li><a href="#trunkSourceJavaScriptCoredisassemblerudis86udis86_udinth">trunk/Source/JavaScriptCore/disassembler/udis86/udis86_udint.h</a></li>
</ul>
<h3>Removed Paths</h3>
<ul>
<li><a href="#trunkSourceJavaScriptCoredisassemblerudis86itabpy">trunk/Source/JavaScriptCore/disassembler/udis86/itab.py</a></li>
<li><a href="#trunkSourceJavaScriptCoredisassemblerudis86ud_optablepy">trunk/Source/JavaScriptCore/disassembler/udis86/ud_optable.py</a></li>
<li><a href="#trunkSourceJavaScriptCoredisassemblerudis86udis86_inputc">trunk/Source/JavaScriptCore/disassembler/udis86/udis86_input.c</a></li>
<li><a href="#trunkSourceJavaScriptCoredisassemblerudis86udis86_inputh">trunk/Source/JavaScriptCore/disassembler/udis86/udis86_input.h</a></li>
</ul>
</div>
<div id="patch">
<h3>Diff</h3>
<a id="trunkSourceJavaScriptCoreCMakeListstxt"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/CMakeLists.txt (198831 => 198832)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/CMakeLists.txt 2016-03-30 07:14:10 UTC (rev 198831)
+++ trunk/Source/JavaScriptCore/CMakeLists.txt 2016-03-30 07:17:14 UTC (rev 198832)
</span><span class="lines">@@ -388,7 +388,6 @@
</span><span class="cx">
</span><span class="cx"> disassembler/udis86/udis86.c
</span><span class="cx"> disassembler/udis86/udis86_decode.c
</span><del>- disassembler/udis86/udis86_input.c
</del><span class="cx"> disassembler/udis86/udis86_itab_holder.c
</span><span class="cx"> disassembler/udis86/udis86_syn-att.c
</span><span class="cx"> disassembler/udis86/udis86_syn-intel.c
</span><span class="lines">@@ -912,14 +911,13 @@
</span><span class="cx">
</span><span class="cx"> set(UDIS_GEN_DEP
</span><span class="cx"> disassembler/udis86/ud_opcode.py
</span><del>- disassembler/udis86/ud_optable.py
</del><span class="cx"> )
</span><span class="cx">
</span><span class="cx"> add_custom_command(
</span><span class="cx"> OUTPUT ${DERIVED_SOURCES_JAVASCRIPTCORE_DIR}/udis86_itab.c ${DERIVED_SOURCES_JAVASCRIPTCORE_DIR}/udis86_itab.h
</span><span class="cx"> DEPENDS ${UDIS_GEN_DEP}
</span><span class="cx"> WORKING_DIRECTORY ${DERIVED_SOURCES_JAVASCRIPTCORE_DIR}
</span><del>- COMMAND ${PYTHON_EXECUTABLE} ${JAVASCRIPTCORE_DIR}/disassembler/udis86/itab.py ${JAVASCRIPTCORE_DIR}/disassembler/udis86/optable.xml
</del><ins>+ COMMAND ${PYTHON_EXECUTABLE} ${JAVASCRIPTCORE_DIR}/disassembler/udis86/ud_itab.py ${JAVASCRIPTCORE_DIR}/disassembler/udis86/optable.xml ${DERIVED_SOURCES_JAVASCRIPTCORE_DIR}
</ins><span class="cx"> VERBATIM)
</span><span class="cx">
</span><span class="cx"> list(APPEND JavaScriptCore_HEADERS
</span></span></pre></div>
<a id="trunkSourceJavaScriptCoreChangeLog"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/ChangeLog (198831 => 198832)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/ChangeLog 2016-03-30 07:14:10 UTC (rev 198831)
+++ trunk/Source/JavaScriptCore/ChangeLog 2016-03-30 07:17:14 UTC (rev 198832)
</span><span class="lines">@@ -1,3 +1,30 @@
</span><ins>+2016-03-30 Benjamin Poulain <benjamin@webkit.org>
+
+ [JSC] Update udis86
+ https://bugs.webkit.org/show_bug.cgi?id=156005
+
+ Reviewed by Geoffrey Garen.
+
+ * CMakeLists.txt:
+ * DerivedSources.make:
+ * JavaScriptCore.xcodeproj/project.pbxproj:
+ * disassembler/udis86/differences.txt:
+ * disassembler/udis86/itab.py: Removed.
+ * disassembler/udis86/optable.xml:
+ * disassembler/udis86/ud_itab.py: Added.
+ * disassembler/udis86/ud_opcode.py:
+ * disassembler/udis86/ud_optable.py: Removed.
+ * disassembler/udis86/udis86.c:
+ * disassembler/udis86/udis86_decode.c:
+ * disassembler/udis86/udis86_decode.h:
+ * disassembler/udis86/udis86_extern.h:
+ * disassembler/udis86/udis86_input.c: Removed.
+ * disassembler/udis86/udis86_input.h: Removed.
+ * disassembler/udis86/udis86_syn-att.c:
+ * disassembler/udis86/udis86_syn.h:
+ * disassembler/udis86/udis86_types.h:
+ * disassembler/udis86/udis86_udint.h:
+
</ins><span class="cx"> 2016-03-30 Benjamin Poulain <bpoulain@apple.com>
</span><span class="cx">
</span><span class="cx"> [JSC] Get rid of operationInitGlobalConst(), it is useless
</span></span></pre></div>
<a id="trunkSourceJavaScriptCoreDerivedSourcesmake"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/DerivedSources.make (198831 => 198832)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/DerivedSources.make 2016-03-30 07:14:10 UTC (rev 198831)
+++ trunk/Source/JavaScriptCore/DerivedSources.make 2016-03-30 07:17:14 UTC (rev 198832)
</span><span class="lines">@@ -172,8 +172,8 @@
</span><span class="cx">
</span><span class="cx"> # udis86 instruction tables
</span><span class="cx">
</span><del>-udis86_itab.h: $(JavaScriptCore)/disassembler/udis86/itab.py $(JavaScriptCore)/disassembler/udis86/optable.xml
- $(PYTHON) $(JavaScriptCore)/disassembler/udis86/itab.py $(JavaScriptCore)/disassembler/udis86/optable.xml
</del><ins>+udis86_itab.h: $(JavaScriptCore)/disassembler/udis86/ud_itab.py $(JavaScriptCore)/disassembler/udis86/optable.xml
+ $(PYTHON) $(JavaScriptCore)/disassembler/udis86/ud_itab.py $(JavaScriptCore)/disassembler/udis86/optable.xml .
</ins><span class="cx">
</span><span class="cx"> # Bytecode files
</span><span class="cx">
</span></span></pre></div>
<a id="trunkSourceJavaScriptCoreJavaScriptCorexcodeprojprojectpbxproj"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/JavaScriptCore.xcodeproj/project.pbxproj (198831 => 198832)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/JavaScriptCore.xcodeproj/project.pbxproj 2016-03-30 07:14:10 UTC (rev 198831)
+++ trunk/Source/JavaScriptCore/JavaScriptCore.xcodeproj/project.pbxproj 2016-03-30 07:17:14 UTC (rev 198832)
</span><span class="lines">@@ -894,8 +894,6 @@
</span><span class="cx"> 0FF42740158EBE8B004CB9FF /* udis86_decode.c in Sources */ = {isa = PBXBuildFile; fileRef = 0FF42734158EBD94004CB9FF /* udis86_decode.c */; };
</span><span class="cx"> 0FF42741158EBE8D004CB9FF /* udis86_decode.h in Headers */ = {isa = PBXBuildFile; fileRef = 0FF42735158EBD94004CB9FF /* udis86_decode.h */; };
</span><span class="cx"> 0FF42742158EBE91004CB9FF /* udis86_extern.h in Headers */ = {isa = PBXBuildFile; fileRef = 0FF42736158EBD94004CB9FF /* udis86_extern.h */; };
</span><del>- 0FF42743158EBE91004CB9FF /* udis86_input.c in Sources */ = {isa = PBXBuildFile; fileRef = 0FF42737158EBD94004CB9FF /* udis86_input.c */; };
- 0FF42744158EBE91004CB9FF /* udis86_input.h in Headers */ = {isa = PBXBuildFile; fileRef = 0FF42738158EBD94004CB9FF /* udis86_input.h */; };
</del><span class="cx"> 0FF42745158EBE91004CB9FF /* udis86_syn-att.c in Sources */ = {isa = PBXBuildFile; fileRef = 0FF42739158EBD94004CB9FF /* udis86_syn-att.c */; };
</span><span class="cx"> 0FF42746158EBE91004CB9FF /* udis86_syn-intel.c in Sources */ = {isa = PBXBuildFile; fileRef = 0FF4273A158EBD94004CB9FF /* udis86_syn-intel.c */; };
</span><span class="cx"> 0FF42747158EBE91004CB9FF /* udis86_syn.c in Sources */ = {isa = PBXBuildFile; fileRef = 0FF4273B158EBD94004CB9FF /* udis86_syn.c */; };
</span><span class="lines">@@ -3053,8 +3051,6 @@
</span><span class="cx"> 0FF42734158EBD94004CB9FF /* udis86_decode.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = udis86_decode.c; path = disassembler/udis86/udis86_decode.c; sourceTree = "<group>"; };
</span><span class="cx"> 0FF42735158EBD94004CB9FF /* udis86_decode.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = udis86_decode.h; path = disassembler/udis86/udis86_decode.h; sourceTree = "<group>"; };
</span><span class="cx"> 0FF42736158EBD94004CB9FF /* udis86_extern.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = udis86_extern.h; path = disassembler/udis86/udis86_extern.h; sourceTree = "<group>"; };
</span><del>- 0FF42737158EBD94004CB9FF /* udis86_input.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = udis86_input.c; path = disassembler/udis86/udis86_input.c; sourceTree = "<group>"; };
- 0FF42738158EBD94004CB9FF /* udis86_input.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = udis86_input.h; path = disassembler/udis86/udis86_input.h; sourceTree = "<group>"; };
</del><span class="cx"> 0FF42739158EBD94004CB9FF /* udis86_syn-att.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = "udis86_syn-att.c"; path = "disassembler/udis86/udis86_syn-att.c"; sourceTree = "<group>"; };
</span><span class="cx"> 0FF4273A158EBD94004CB9FF /* udis86_syn-intel.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = "udis86_syn-intel.c"; path = "disassembler/udis86/udis86_syn-intel.c"; sourceTree = "<group>"; };
</span><span class="cx"> 0FF4273B158EBD94004CB9FF /* udis86_syn.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = udis86_syn.c; path = disassembler/udis86/udis86_syn.c; sourceTree = "<group>"; };
</span><span class="lines">@@ -3281,6 +3277,7 @@
</span><span class="cx"> 43AB26C41C1A52F700D82AE6 /* B3MathExtras.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; name = B3MathExtras.cpp; path = b3/B3MathExtras.cpp; sourceTree = "<group>"; };
</span><span class="cx"> 43AB26C51C1A52F700D82AE6 /* B3MathExtras.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = B3MathExtras.h; path = b3/B3MathExtras.h; sourceTree = "<group>"; };
</span><span class="cx"> 43C392AA1C3BEB0000241F53 /* AssemblerCommon.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = AssemblerCommon.h; sourceTree = "<group>"; };
</span><ins>+ 43CBA1601CAB67BA00328A5C /* udis86_udint.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = udis86_udint.h; path = disassembler/udis86/udis86_udint.h; sourceTree = "<group>"; };
</ins><span class="cx"> 449097EE0F8F81B50076A327 /* FeatureDefines.xcconfig */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text.xcconfig; path = FeatureDefines.xcconfig; sourceTree = "<group>"; };
</span><span class="cx"> 451539B812DC994500EF7AC4 /* Yarr.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = Yarr.h; path = yarr/Yarr.h; sourceTree = "<group>"; };
</span><span class="cx"> 45E12D8806A49B0F00E9DF84 /* jsc.cpp */ = {isa = PBXFileReference; fileEncoding = 30; indentWidth = 4; lastKnownFileType = sourcecode.cpp.cpp; path = jsc.cpp; sourceTree = "<group>"; tabWidth = 4; };
</span><span class="lines">@@ -4884,9 +4881,8 @@
</span><span class="cx"> 0FF42734158EBD94004CB9FF /* udis86_decode.c */,
</span><span class="cx"> 0FF42735158EBD94004CB9FF /* udis86_decode.h */,
</span><span class="cx"> 0FF42736158EBD94004CB9FF /* udis86_extern.h */,
</span><del>- 0FF42737158EBD94004CB9FF /* udis86_input.c */,
- 0FF42738158EBD94004CB9FF /* udis86_input.h */,
</del><span class="cx"> 0FF4274C158EBFE1004CB9FF /* udis86_itab_holder.c */,
</span><ins>+ 43CBA1601CAB67BA00328A5C /* udis86_udint.h */,
</ins><span class="cx"> 0FF42739158EBD94004CB9FF /* udis86_syn-att.c */,
</span><span class="cx"> 0FF4273A158EBD94004CB9FF /* udis86_syn-intel.c */,
</span><span class="cx"> 0FF4273B158EBD94004CB9FF /* udis86_syn.c */,
</span><span class="lines">@@ -8016,7 +8012,6 @@
</span><span class="cx"> 0FF4274B158EBE91004CB9FF /* udis86.h in Headers */,
</span><span class="cx"> 0FF42741158EBE8D004CB9FF /* udis86_decode.h in Headers */,
</span><span class="cx"> 0FF42742158EBE91004CB9FF /* udis86_extern.h in Headers */,
</span><del>- 0FF42744158EBE91004CB9FF /* udis86_input.h in Headers */,
</del><span class="cx"> 0FF42748158EBE91004CB9FF /* udis86_syn.h in Headers */,
</span><span class="cx"> 0FF42749158EBE91004CB9FF /* udis86_types.h in Headers */,
</span><span class="cx"> A7E5AB391799E4B200D2833D /* UDis86Disassembler.h in Headers */,
</span><span class="lines">@@ -9328,7 +9323,6 @@
</span><span class="cx"> 0F6B8AE41C4EFE1700969052 /* B3FixSSA.cpp in Sources */,
</span><span class="cx"> 0FF4274A158EBE91004CB9FF /* udis86.c in Sources */,
</span><span class="cx"> 0FF42740158EBE8B004CB9FF /* udis86_decode.c in Sources */,
</span><del>- 0FF42743158EBE91004CB9FF /* udis86_input.c in Sources */,
</del><span class="cx"> FEA1E4391C213A2B00277A16 /* ValueProfile.cpp in Sources */,
</span><span class="cx"> 0FF4274D158EBFE6004CB9FF /* udis86_itab_holder.c in Sources */,
</span><span class="cx"> 0FF42745158EBE91004CB9FF /* udis86_syn-att.c in Sources */,
</span></span></pre></div>
<a id="trunkSourceJavaScriptCoredisassemblerudis86differencestxt"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/disassembler/udis86/differences.txt (198831 => 198832)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/disassembler/udis86/differences.txt 2016-03-30 07:14:10 UTC (rev 198831)
+++ trunk/Source/JavaScriptCore/disassembler/udis86/differences.txt 2016-03-30 07:17:14 UTC (rev 198832)
</span><span class="lines">@@ -5,20 +5,5 @@
</span><span class="cx">
</span><span class="cx"> - assert() has been changed to ASSERT()
</span><span class="cx">
</span><del>-- Mass rename of udis86_input.h inp_ prefixed functions and macros to ud_inp_ to
- avoid namespace pollution.
-
-- Removal of KERNEL checks.
-
-- Added #include of udis86_extern.h in udis86_decode.c.
-
-- Removed s_ie__pause and s_ie__nop from udis86_decode.c, since they weren't used.
-
-- Made udis86_syn.h use WTF_ATTRIBUTE_PRINTF. This required making a bunch of little
- fixes to make the compiler's format string warnings go away.
-
-- Made the code in udis86_syn.h use vsnprintf() instead of vsprintf().
-
</del><span class="cx"> - Fixed udis86_syn-att.c's jump destination printing to work correctly in 64-bit mode.
</span><span class="cx">
</span><del>-- Add --outputDir option to itab.py.
</del></span></pre></div>
<a id="trunkSourceJavaScriptCoredisassemblerudis86itabpy"></a>
<div class="delfile"><h4>Deleted: trunk/Source/JavaScriptCore/disassembler/udis86/itab.py (198831 => 198832)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/disassembler/udis86/itab.py 2016-03-30 07:14:10 UTC (rev 198831)
+++ trunk/Source/JavaScriptCore/disassembler/udis86/itab.py 2016-03-30 07:17:14 UTC (rev 198832)
</span><span class="lines">@@ -1,360 +0,0 @@
</span><del>-# udis86 - scripts/itab.py
-#
-# Copyright (c) 2009 Vivek Thampi
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without modification,
-# are permitted provided that the following conditions are met:
-#
-# * Redistributions of source code must retain the above copyright notice,
-# this list of conditions and the following disclaimer.
-# * Redistributions in binary form must reproduce the above copyright notice,
-# this list of conditions and the following disclaimer in the documentation
-# and/or other materials provided with the distribution.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-from optparse import OptionParser
-import os
-import sys
-
-sys.path.append( '../scripts' );
-
-import ud_optable
-import ud_opcode
-
-class UdItabGenerator( ud_opcode.UdOpcodeTables ):
-
- OperandDict = {
- "Ap" : [ "OP_A" , "SZ_P" ],
- "E" : [ "OP_E" , "SZ_NA" ],
- "Eb" : [ "OP_E" , "SZ_B" ],
- "Ew" : [ "OP_E" , "SZ_W" ],
- "Ev" : [ "OP_E" , "SZ_V" ],
- "Ed" : [ "OP_E" , "SZ_D" ],
- "Eq" : [ "OP_E" , "SZ_Q" ],
- "Ez" : [ "OP_E" , "SZ_Z" ],
- "Ex" : [ "OP_E" , "SZ_MDQ" ],
- "Ep" : [ "OP_E" , "SZ_P" ],
- "G" : [ "OP_G" , "SZ_NA" ],
- "Gb" : [ "OP_G" , "SZ_B" ],
- "Gw" : [ "OP_G" , "SZ_W" ],
- "Gv" : [ "OP_G" , "SZ_V" ],
- "Gy" : [ "OP_G" , "SZ_MDQ" ],
- "Gy" : [ "OP_G" , "SZ_MDQ" ],
- "Gd" : [ "OP_G" , "SZ_D" ],
- "Gq" : [ "OP_G" , "SZ_Q" ],
- "Gx" : [ "OP_G" , "SZ_MDQ" ],
- "Gz" : [ "OP_G" , "SZ_Z" ],
- "M" : [ "OP_M" , "SZ_NA" ],
- "Mb" : [ "OP_M" , "SZ_B" ],
- "Mw" : [ "OP_M" , "SZ_W" ],
- "Ms" : [ "OP_M" , "SZ_W" ],
- "Md" : [ "OP_M" , "SZ_D" ],
- "Mq" : [ "OP_M" , "SZ_Q" ],
- "Mt" : [ "OP_M" , "SZ_T" ],
- "Mo" : [ "OP_M" , "SZ_O" ],
- "MwRv" : [ "OP_MR" , "SZ_WV" ],
- "MdRy" : [ "OP_MR" , "SZ_DY" ],
- "MbRv" : [ "OP_MR" , "SZ_BV" ],
- "I1" : [ "OP_I1" , "SZ_NA" ],
- "I3" : [ "OP_I3" , "SZ_NA" ],
- "Ib" : [ "OP_I" , "SZ_B" ],
- "Isb" : [ "OP_I" , "SZ_SB" ],
- "Iw" : [ "OP_I" , "SZ_W" ],
- "Iv" : [ "OP_I" , "SZ_V" ],
- "Iz" : [ "OP_I" , "SZ_Z" ],
- "Jv" : [ "OP_J" , "SZ_V" ],
- "Jz" : [ "OP_J" , "SZ_Z" ],
- "Jb" : [ "OP_J" , "SZ_B" ],
- "R" : [ "OP_R" , "SZ_RDQ" ],
- "C" : [ "OP_C" , "SZ_NA" ],
- "D" : [ "OP_D" , "SZ_NA" ],
- "S" : [ "OP_S" , "SZ_NA" ],
- "Ob" : [ "OP_O" , "SZ_B" ],
- "Ow" : [ "OP_O" , "SZ_W" ],
- "Ov" : [ "OP_O" , "SZ_V" ],
- "V" : [ "OP_V" , "SZ_O" ],
- "W" : [ "OP_W" , "SZ_O" ],
- "Wsd" : [ "OP_W" , "SZ_O" ],
- "Wss" : [ "OP_W" , "SZ_O" ],
- "P" : [ "OP_P" , "SZ_Q" ],
- "Q" : [ "OP_Q" , "SZ_Q" ],
- "VR" : [ "OP_VR" , "SZ_O" ],
- "PR" : [ "OP_PR" , "SZ_Q" ],
- "AL" : [ "OP_AL" , "SZ_NA" ],
- "CL" : [ "OP_CL" , "SZ_NA" ],
- "DL" : [ "OP_DL" , "SZ_NA" ],
- "BL" : [ "OP_BL" , "SZ_NA" ],
- "AH" : [ "OP_AH" , "SZ_NA" ],
- "CH" : [ "OP_CH" , "SZ_NA" ],
- "DH" : [ "OP_DH" , "SZ_NA" ],
- "BH" : [ "OP_BH" , "SZ_NA" ],
- "AX" : [ "OP_AX" , "SZ_NA" ],
- "CX" : [ "OP_CX" , "SZ_NA" ],
- "DX" : [ "OP_DX" , "SZ_NA" ],
- "BX" : [ "OP_BX" , "SZ_NA" ],
- "SI" : [ "OP_SI" , "SZ_NA" ],
- "DI" : [ "OP_DI" , "SZ_NA" ],
- "SP" : [ "OP_SP" , "SZ_NA" ],
- "BP" : [ "OP_BP" , "SZ_NA" ],
- "eAX" : [ "OP_eAX" , "SZ_NA" ],
- "eCX" : [ "OP_eCX" , "SZ_NA" ],
- "eDX" : [ "OP_eDX" , "SZ_NA" ],
- "eBX" : [ "OP_eBX" , "SZ_NA" ],
- "eSI" : [ "OP_eSI" , "SZ_NA" ],
- "eDI" : [ "OP_eDI" , "SZ_NA" ],
- "eSP" : [ "OP_eSP" , "SZ_NA" ],
- "eBP" : [ "OP_eBP" , "SZ_NA" ],
- "rAX" : [ "OP_rAX" , "SZ_NA" ],
- "rCX" : [ "OP_rCX" , "SZ_NA" ],
- "rBX" : [ "OP_rBX" , "SZ_NA" ],
- "rDX" : [ "OP_rDX" , "SZ_NA" ],
- "rSI" : [ "OP_rSI" , "SZ_NA" ],
- "rDI" : [ "OP_rDI" , "SZ_NA" ],
- "rSP" : [ "OP_rSP" , "SZ_NA" ],
- "rBP" : [ "OP_rBP" , "SZ_NA" ],
- "ES" : [ "OP_ES" , "SZ_NA" ],
- "CS" : [ "OP_CS" , "SZ_NA" ],
- "DS" : [ "OP_DS" , "SZ_NA" ],
- "SS" : [ "OP_SS" , "SZ_NA" ],
- "GS" : [ "OP_GS" , "SZ_NA" ],
- "FS" : [ "OP_FS" , "SZ_NA" ],
- "ST0" : [ "OP_ST0" , "SZ_NA" ],
- "ST1" : [ "OP_ST1" , "SZ_NA" ],
- "ST2" : [ "OP_ST2" , "SZ_NA" ],
- "ST3" : [ "OP_ST3" , "SZ_NA" ],
- "ST4" : [ "OP_ST4" , "SZ_NA" ],
- "ST5" : [ "OP_ST5" , "SZ_NA" ],
- "ST6" : [ "OP_ST6" , "SZ_NA" ],
- "ST7" : [ "OP_ST7" , "SZ_NA" ],
- "NONE" : [ "OP_NONE" , "SZ_NA" ],
- "ALr8b" : [ "OP_ALr8b" , "SZ_NA" ],
- "CLr9b" : [ "OP_CLr9b" , "SZ_NA" ],
- "DLr10b" : [ "OP_DLr10b" , "SZ_NA" ],
- "BLr11b" : [ "OP_BLr11b" , "SZ_NA" ],
- "AHr12b" : [ "OP_AHr12b" , "SZ_NA" ],
- "CHr13b" : [ "OP_CHr13b" , "SZ_NA" ],
- "DHr14b" : [ "OP_DHr14b" , "SZ_NA" ],
- "BHr15b" : [ "OP_BHr15b" , "SZ_NA" ],
- "rAXr8" : [ "OP_rAXr8" , "SZ_NA" ],
- "rCXr9" : [ "OP_rCXr9" , "SZ_NA" ],
- "rDXr10" : [ "OP_rDXr10" , "SZ_NA" ],
- "rBXr11" : [ "OP_rBXr11" , "SZ_NA" ],
- "rSPr12" : [ "OP_rSPr12" , "SZ_NA" ],
- "rBPr13" : [ "OP_rBPr13" , "SZ_NA" ],
- "rSIr14" : [ "OP_rSIr14" , "SZ_NA" ],
- "rDIr15" : [ "OP_rDIr15" , "SZ_NA" ],
- "jWP" : [ "OP_J" , "SZ_WP" ],
- "jDP" : [ "OP_J" , "SZ_DP" ],
-
- }
-
- #
- # opcode prefix dictionary
- #
- PrefixDict = {
- "aso" : "P_aso",
- "oso" : "P_oso",
- "rexw" : "P_rexw",
- "rexb" : "P_rexb",
- "rexx" : "P_rexx",
- "rexr" : "P_rexr",
- "seg" : "P_seg",
- "inv64" : "P_inv64",
- "def64" : "P_def64",
- "depM" : "P_depM",
- "cast1" : "P_c1",
- "cast2" : "P_c2",
- "cast3" : "P_c3",
- "cast" : "P_cast",
- "sext" : "P_sext"
- }
-
- InvalidEntryIdx = 0
- InvalidEntry = { 'type' : 'invalid',
- 'mnemonic' : 'invalid',
- 'operands' : '',
- 'prefixes' : '',
- 'meta' : '' }
-
- Itab = [] # instruction table
- ItabIdx = 1 # instruction table index
- GtabIdx = 0 # group table index
- GtabMeta = []
-
- ItabLookup = {}
-
- MnemonicAliases = ( "invalid", "3dnow", "none", "db", "pause" )
-
- def __init__( self, outputDir ):
- # first itab entry (0) is Invalid
- self.Itab.append( self.InvalidEntry )
- self.MnemonicsTable.extend( self.MnemonicAliases )
- self.outputDir = outputDir
-
- def toGroupId( self, id ):
- return 0x8000 | id
-
- def genLookupTable( self, table, scope = '' ):
- idxArray = [ ]
- ( tabIdx, self.GtabIdx ) = ( self.GtabIdx, self.GtabIdx + 1 )
- self.GtabMeta.append( { 'type' : table[ 'type' ], 'meta' : table[ 'meta' ] } )
-
- for _idx in range( self.sizeOfTable( table[ 'type' ] ) ):
- idx = "%02x" % _idx
-
- e = self.InvalidEntry
- i = self.InvalidEntryIdx
-
- if idx in table[ 'entries' ].keys():
- e = table[ 'entries' ][ idx ]
-
- # leaf node (insn)
- if e[ 'type' ] == 'insn':
- ( i, self.ItabIdx ) = ( self.ItabIdx, self.ItabIdx + 1 )
- self.Itab.append( e )
- elif e[ 'type' ] != 'invalid':
- i = self.genLookupTable( e, 'static' )
-
- idxArray.append( i )
-
- name = "ud_itab__%s" % tabIdx
- self.ItabLookup[ tabIdx ] = name
-
- self.ItabC.write( "\n" );
- if len( scope ):
- self.ItabC.write( scope + ' ' )
- self.ItabC.write( "const uint16_t %s[] = {\n" % name )
- for i in range( len( idxArray ) ):
- if i > 0 and i % 4 == 0:
- self.ItabC.write( "\n" )
- if ( i%4 == 0 ):
- self.ItabC.write( " /* %2x */" % i)
- if idxArray[ i ] >= 0x8000:
- self.ItabC.write( "%12s," % ("GROUP(%d)" % ( ~0x8000 & idxArray[ i ] )))
- else:
- self.ItabC.write( "%12d," % ( idxArray[ i ] ))
- self.ItabC.write( "\n" )
- self.ItabC.write( "};\n" )
-
- return self.toGroupId( tabIdx )
-
- def genLookupTableList( self ):
- self.ItabC.write( "\n\n" );
- self.ItabC.write( "struct ud_lookup_table_list_entry ud_lookup_table_list[] = {\n" )
- for i in range( len( self.GtabMeta ) ):
- f0 = self.ItabLookup[ i ] + ","
- f1 = ( self.nameOfTable( self.GtabMeta[ i ][ 'type' ] ) ) + ","
- f2 = "\"%s\"" % self.GtabMeta[ i ][ 'meta' ]
- self.ItabC.write( " /* %03d */ { %s %s %s },\n" % ( i, f0, f1, f2 ) )
- self.ItabC.write( "};" )
-
- def genInsnTable( self ):
- self.ItabC.write( "struct ud_itab_entry ud_itab[] = {\n" );
- idx = 0
- for e in self.Itab:
- opr_c = [ "O_NONE", "O_NONE", "O_NONE" ]
- pfx_c = []
- opr = e[ 'operands' ]
- for i in range(len(opr)):
- if not (opr[i] in self.OperandDict.keys()):
- print("error: invalid operand declaration: %s\n" % opr[i])
- opr_c[i] = "O_" + opr[i]
- opr = "%s %s %s" % (opr_c[0] + ",", opr_c[1] + ",", opr_c[2])
-
- for p in e['prefixes']:
- if not ( p in self.PrefixDict.keys() ):
- print("error: invalid prefix specification: %s \n" % pfx)
- pfx_c.append( self.PrefixDict[p] )
- if len(e['prefixes']) == 0:
- pfx_c.append( "P_none" )
- pfx = "|".join( pfx_c )
-
- self.ItabC.write( " /* %04d */ { UD_I%s %s, %s },\n" \
- % ( idx, e[ 'mnemonic' ] + ',', opr, pfx ) )
- idx += 1
- self.ItabC.write( "};\n" )
-
- self.ItabC.write( "\n\n" );
- self.ItabC.write( "const char * ud_mnemonics_str[] = {\n" )
- self.ItabC.write( ",\n ".join( [ "\"%s\"" % m for m in self.MnemonicsTable ] ) )
- self.ItabC.write( "\n};\n" )
-
-
- def genItabH( self ):
- self.ItabH = open( os.path.join(self.outputDir, "udis86_itab.h"), "w" )
-
- # Generate Table Type Enumeration
- self.ItabH.write( "#ifndef UD_ITAB_H\n" )
- self.ItabH.write( "#define UD_ITAB_H\n\n" )
-
- # table type enumeration
- self.ItabH.write( "/* ud_table_type -- lookup table types (see lookup.c) */\n" )
- self.ItabH.write( "enum ud_table_type {\n " )
- enum = [ self.TableInfo[ k ][ 'name' ] for k in self.TableInfo.keys() ]
- self.ItabH.write( ",\n ".join( enum ) )
- self.ItabH.write( "\n};\n\n" );
-
- # mnemonic enumeration
- self.ItabH.write( "/* ud_mnemonic -- mnemonic constants */\n" )
- enum = "enum ud_mnemonic_code {\n "
- enum += ",\n ".join( [ "UD_I%s" % m for m in self.MnemonicsTable ] )
- enum += "\n} UD_ATTR_PACKED;\n"
- self.ItabH.write( enum )
- self.ItabH.write( "\n" )
-
- self.ItabH.write("\n/* itab entry operand definitions */\n");
- operands = self.OperandDict.keys()
- operands.sort()
- for o in operands:
- self.ItabH.write("#define O_%-7s { %-12s %-8s }\n" %
- (o, self.OperandDict[o][0] + ",", self.OperandDict[o][1]));
- self.ItabH.write("\n\n");
-
- self.ItabH.write( "extern const char * ud_mnemonics_str[];\n" )
-
- self.ItabH.write( "#define GROUP(n) (0x8000 | (n))" )
-
- self.ItabH.write( "\n#endif /* UD_ITAB_H */\n" )
-
- self.ItabH.close()
-
-
- def genItabC( self ):
- self.ItabC = open( os.path.join(self.outputDir, "udis86_itab.c"), "w" )
- self.ItabC.write( "/* itab.c -- generated by itab.py, do no edit" )
- self.ItabC.write( " */\n" );
- self.ItabC.write( "#include \"udis86_decode.h\"\n\n" );
-
- self.genLookupTable( self.OpcodeTable0 )
- self.genLookupTableList()
- self.genInsnTable()
-
- self.ItabC.close()
-
- def genItab( self ):
- self.genItabC()
- self.genItabH()
-
-def main():
- parser = OptionParser()
- parser.add_option("--outputDir", dest="outputDir", default="")
- options, args = parser.parse_args()
- generator = UdItabGenerator(os.path.normpath(options.outputDir))
- optableXmlParser = ud_optable.UdOptableXmlParser()
- optableXmlParser.parse( args[ 0 ], generator.addInsnDef )
-
- generator.genItab()
-
-if __name__ == '__main__':
- main()
</del></span></pre></div>
<a id="trunkSourceJavaScriptCoredisassemblerudis86optablexml"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/disassembler/udis86/optable.xml (198831 => 198832)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/disassembler/udis86/optable.xml 2016-03-30 07:14:10 UTC (rev 198831)
+++ trunk/Source/JavaScriptCore/disassembler/udis86/optable.xml 2016-03-30 07:17:14 UTC (rev 198832)
</span><span class="lines">@@ -2,37 +2,132 @@
</span><span class="cx"> <?xml-stylesheet href="optable.xsl" type="text/xsl"?>
</span><span class="cx"> <x86optable>
</span><span class="cx">
</span><ins>+ <!--
+ The most important elements of each instruction definition are the
+ pfx (prefix), opc (opcode), and opr (operand) elements. Each is a
+ CDATA element consisting of blank-separated words. Upper and lower
+ case are equivalent.
+
+ <pfx></pfx>
+
+ pfx describes the set of valid prefixes that can precede the main
+ opcode without turning it into a different instruction. These may
+ be:
+
+ aso accepts address size override
+ oso accepts operand size override
+ seg accepts a segment override
+ rexw, rexr, rexx, rexb
+ uses the indicated REX bit
+ vexl accepts the vex.L prefix bit, in other words, the vexl
+ bit can be used in the decoding of the avx instruction.
+
+ <opr></opr>
+
+ [T][s]
+
+ Size Suffix
+ ===========
+
+ x - If vex.L = 1 => m256/YMM
+ vex.L = 0 => m128/XMM
+
+ opc words may be actual byte values (two hex digits), or may be one of
+ the following:
+ /sse=66,f3,f2 - required prefix (always first, and always
+ followed by 0f)
+ /3dnow=00-ff - this is a 3DNow opcode (only in a definition of the
+ form 0f 0f 3dnow=<byte>)
+ /a=16,32,64 - has this address size
+ /m=16,32,64,!64 - applicable only when the CPU is in this mode
+ /o=16,32,64 - has this operand size
+ /mod=11,!11 - has ModR/M with 11 or not-11 in the Mod field
+ /reg=0-7 - has ModR/M with this value in the reg field
+ /rm=0-7 - has ModR/M with this value in the R/M field (only with
+ /mod=11)
+ /x87=00-3f - X87 opcode with this value in the low 6 bits of the
+ following "ModR/M" byte (only with /mod=11 and no other modifiers)
+
+ opr words follow the Intel documentation somewhat, and specify the
+ location and the size of the operand. The OperandDict table in
+ ud_itab.py maps these words to named OP_ and SZ_ constants for the
+ location and size respectively. These constants are defined in
+ decode.h, q.v. for details.
+
+ The mode element affects instruction semantics but not decoding:
+ inv64 - invalid in 64-bit mode
+ def64 - default operand size is 64 bits in 64-bit mode
+
+ cpuid
+
+ The cpuid element maybe applied to an instruction or a specific
+ definition of the instruction. One ore more strings define the
+ cpuid features that the instruction (or a definition belongs to)
+
+ Values are: sse, sse2, sse3, sse4, sse4.1, sse4.2, avx
+
+ AVX Instructions
+
+ AVX instructions can be described in two ways. One, the explicit
+ form, and the other that promotes an existing sse instruction
+ definition to its avx form.
+
+ If an instruction is defined to be in cpuid=avx, but is defined in
+ the legacy form (using /sse= extensions), then the opcode generator
+ will infer that as two definitions, one the see instruction and the
+ other, an inferred avx instruction.
+
+ In generating the sse definition from the above, the following
+ transformations happen,
+
+ - /vexw and /vexl extensions (if any) are removed
+ - The operands H and L are removed. Operands specified on
+ the right to removed operands are shifted to the left
+ position.
+ - The vexl prefix is removed.
+ - "avx" is removed form the cpuid definition.
+
+ In generating the avx definition from the above, the following
+ transformations happen,
+
+ - c4 is inserted in the 0th position of the opcode string
+ - /sse extension is removed
+ - A new /vex extension is constructed using /sse, 0f, 38 and
+ 3a opcodes (if any).
+ - Operands V, W, H, and U are marked explicitly to have the
+ size suffix "x"
+
+ If the above transformations do not generate the required
+ definitions, the instructions will need to be defined separately.
+ -->
+
</ins><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>aaa</mnemonic>
</span><span class="cx"> <def>
</span><del>- <opc>37</opc>
- <mode>inv64</mode>
</del><ins>+ <opc>37 /m=!64</opc>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>aad</mnemonic>
</span><span class="cx"> <def>
</span><del>- <opc>d5</opc>
</del><ins>+ <opc>d5 /m=!64</opc>
</ins><span class="cx"> <opr>Ib</opr>
</span><del>- <mode>inv64</mode>
</del><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>aam</mnemonic>
</span><span class="cx"> <def>
</span><del>- <opc>d4</opc>
</del><ins>+ <opc>d4 /m=!64</opc>
</ins><span class="cx"> <opr>Ib</opr>
</span><del>- <mode>inv64</mode>
</del><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>aas</mnemonic>
</span><span class="cx"> <def>
</span><del>- <opc>3f</opc>
- <mode>inv64</mode>
</del><ins>+ <opc>3f /m=!64</opc>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -65,8 +160,7 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexw</pfx>
</span><span class="cx"> <opc>15</opc>
</span><del>- <opr>rAX Iz</opr>
- <syn>sext</syn>
</del><ins>+ <opr>rAX sIz</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -75,21 +169,19 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>82 /reg=2</opc>
</del><ins>+ <opc>82 /reg=2 /m=!64</opc>
</ins><span class="cx"> <opr>Eb Ib</opr>
</span><span class="cx"> <mode>inv64</mode>
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>81 /reg=2</opc>
</span><del>- <opr>Ev Iz</opr>
- <syn>sext</syn>
</del><ins>+ <opr>Ev sIz</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>83 /reg=2</opc>
</span><del>- <opr>Ev Ib</opr>
- <syn>sext</syn>
</del><ins>+ <opr>Ev sIb</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -122,8 +214,7 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexw</pfx>
</span><span class="cx"> <opc>05</opc>
</span><del>- <opr>rAX Iz</opr>
- <syn>sext</syn>
</del><ins>+ <opr>rAX sIz</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -132,43 +223,39 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>82 /reg=0</opc>
</del><ins>+ <opc>82 /reg=0 /m=!64</opc>
</ins><span class="cx"> <opr>Eb Ib</opr>
</span><span class="cx"> <mode>inv64</mode>
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>81 /reg=0</opc>
</span><del>- <opr>Ev Iz</opr>
- <syn>sext</syn>
</del><ins>+ <opr>Ev sIz</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>83 /reg=0</opc>
</span><del>- <opr>Ev Ib</opr>
- <syn>sext</syn>
</del><ins>+ <opr>Ev sIb</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><del>- <!--
- SSE2
- -->
-
</del><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>addpd</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 58</opc>
- <opr>V W</opr>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 58</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>addps</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
</ins><span class="cx"> <opc>0f 58</opc>
</span><del>- <opr>V W</opr>
</del><ins>+ <opr>V H W</opr>
+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -176,8 +263,9 @@
</span><span class="cx"> <mnemonic>addsd</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>ssef2 0f 58</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=f2 0f 58</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -185,12 +273,94 @@
</span><span class="cx"> <mnemonic>addss</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>ssef3 0f 58</opc>
</del><ins>+ <opc>/sse=f3 0f 58</opc>
+ <opr>V H W</opr>
+ <cpuid>sse avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>addsubpd</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb</pfx>
+ <opc>/sse=66 0f d0</opc>
+ <opr>V H W</opr>
+ <cpuid>sse3 avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>addsubps</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb</pfx>
+ <opc>/sse=f2 0f d0</opc>
+ <opr>V H W</opr>
+ <cpuid>sse3 avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>aesdec</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb</pfx>
+ <opc>/sse=66 0f 38 de</opc>
+ <opr>V H W</opr>
+ <cpuid>aesni avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>aesdeclast</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb</pfx>
+ <opc>/sse=66 0f 38 df</opc>
</ins><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>aesni avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><del>- <instruction>
</del><ins>+ <instruction>
+ <mnemonic>aesenc</mnemonic>
+ <cpuid>aesni</cpuid>
+ <def>
+ <pfx>aso rexr rexx rexb</pfx>
+ <opc>/sse=66 0f 38 dc</opc>
+ <opr>V W</opr>
+ <cpuid>aesni avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>aesenclast</mnemonic>
+ <cpuid>aesni avx</cpuid>
+ <def>
+ <pfx>aso rexr rexx rexb</pfx>
+ <opc>/sse=66 0f 38 dd</opc>
+ <opr>V H W</opr>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>aesimc</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb</pfx>
+ <opc>/sse=66 0f 38 db</opc>
+ <opr>V W</opr>
+ <cpuid>aesni avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>aeskeygenassist</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb</pfx>
+ <opc>/sse=66 0f 3a df</opc>
+ <opr>V W Ib</opr>
+ <cpuid>aesni avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
</ins><span class="cx"> <mnemonic>and</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -219,8 +389,7 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexw</pfx>
</span><span class="cx"> <opc>25</opc>
</span><del>- <opr>rAX Iz</opr>
- <syn>sext</syn>
</del><ins>+ <opr>rAX sIz</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexw rexr rexx rexb</pfx>
</span><span class="lines">@@ -229,30 +398,29 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>82 /reg=4</opc>
</del><ins>+ <opc>82 /reg=4 /m=!64</opc>
</ins><span class="cx"> <opr>Eb Ib</opr>
</span><span class="cx"> <mode>inv64</mode>
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>81 /reg=4</opc>
</span><del>- <opr>Ev Iz</opr>
- <syn>sext</syn>
</del><ins>+ <opr>Ev sIz</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>83 /reg=4</opc>
</span><del>- <opr>Ev Ib</opr>
- <syn>sext</syn>
</del><ins>+ <opr>Ev sIb</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>andpd</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 54</opc>
- <opr>V W</opr>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 54</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -261,7 +429,8 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>0f 54</opc>
</span><del>- <opr>V W</opr>
</del><ins>+ <opr>V H W</opr>
+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -269,8 +438,9 @@
</span><span class="cx"> <mnemonic>andnpd</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 55</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 55</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -279,7 +449,8 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>0f 55</opc>
</span><del>- <opr>V W</opr>
</del><ins>+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -287,16 +458,9 @@
</span><span class="cx"> <mnemonic>arpl</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso</pfx>
</span><del>- <opc>63 /m=16</opc>
</del><ins>+ <opc>63 /m=!64</opc>
</ins><span class="cx"> <opr>Ew Gw</opr>
</span><del>- <mode>inv64</mode>
</del><span class="cx"> </def>
</span><del>- <def>
- <pfx>aso</pfx>
- <opc>63 /m=32</opc>
- <opr>Ew Gw</opr>
- <mode>inv64</mode>
- </def>
</del><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="lines">@@ -304,150 +468,27 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexx rexr rexb</pfx>
</span><span class="cx"> <opc>63 /m=64</opc>
</span><del>- <opr>Gv Ed</opr>
</del><ins>+ <opr>Gq Ed</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><del>- <mnemonic>bound</mnemonic>
</del><ins>+ <mnemonic>call</mnemonic>
</ins><span class="cx"> <def>
</span><del>- <pfx>aso oso</pfx>
- <opc>62</opc>
- <opr>Gv M</opr>
- <mode>inv64</mode>
- </def>
- </instruction>
-
- <instruction>
- <mnemonic>bsf</mnemonic>
- <def>
</del><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><del>- <opc>0f bc</opc>
- <opr>Gv Ev</opr>
</del><ins>+ <opc>ff /reg=2 /m=!64</opc>
+ <opr>Ev</opr>
</ins><span class="cx"> </def>
</span><del>- </instruction>
-
- <instruction>
- <mnemonic>bsr</mnemonic>
</del><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><del>- <opc>0f bd</opc>
- <opr>Gv Ev</opr>
- </def>
- </instruction>
-
- <instruction>
- <mnemonic>bswap</mnemonic>
- <def>
- <pfx>oso rexw rexb</pfx>
- <opc>0f c8</opc>
- <opr>rAXr8</opr>
- </def>
- <def>
- <pfx>oso rexw rexb</pfx>
- <opc>0f c9</opc>
- <opr>rCXr9</opr>
- </def>
- <def>
- <pfx>oso rexw rexb</pfx>
- <opc>0f ca</opc>
- <opr>rDXr10</opr>
- </def>
- <def>
- <pfx>oso rexw rexb</pfx>
- <opc>0f cb</opc>
- <opr>rBXr11</opr>
- </def>
- <def>
- <pfx>oso rexw rexb</pfx>
- <opc>0f cc</opc>
- <opr>rSPr12</opr>
- </def>
- <def>
- <pfx>oso rexw rexb</pfx>
- <opc>0f cd</opc>
- <opr>rBPr13</opr>
- </def>
- <def>
- <pfx>oso rexw rexb</pfx>
- <opc>0f ce</opc>
- <opr>rSIr14</opr>
- </def>
- <def>
- <pfx>oso rexw rexb</pfx>
- <opc>0f cf</opc>
- <opr>rDIr15</opr>
- </def>
- </instruction>
-
- <instruction>
- <mnemonic>bt</mnemonic>
- <def>
- <pfx>aso oso rexw rexr rexx rexb</pfx>
- <opc>0f ba /reg=4</opc>
- <opr>Ev Ib</opr>
- </def>
- <def>
- <pfx>aso oso rexw rexr rexx rexb</pfx>
- <opc>0f a3</opc>
- <opr>Ev Gv</opr>
- </def>
- </instruction>
-
- <instruction>
- <mnemonic>btc</mnemonic>
- <def>
- <pfx>aso oso rexw rexr rexx rexb</pfx>
- <opc>0f bb</opc>
- <opr>Ev Gv</opr>
- </def>
- <def>
- <pfx>aso oso rexw rexr rexx rexb</pfx>
- <opc>0f ba /reg=7</opc>
- <opr>Ev Ib</opr>
- </def>
- </instruction>
-
- <instruction>
- <mnemonic>btr</mnemonic>
- <def>
- <pfx>aso oso rexw rexr rexx rexb</pfx>
- <opc>0f b3</opc>
- <opr>Ev Gv</opr>
- </def>
- <def>
- <pfx>aso oso rexw rexr rexx rexb</pfx>
- <opc>0f ba /reg=6</opc>
- <opr>Ev Ib</opr>
- </def>
- </instruction>
-
- <instruction>
- <mnemonic>bts</mnemonic>
- <def>
- <pfx>aso oso rexw rexr rexx rexb</pfx>
- <opc>0f ab</opc>
- <opr>Ev Gv</opr>
- </def>
- <def>
- <pfx>aso oso rexw rexr rexx rexb</pfx>
- <opc>0f ba /reg=5</opc>
- <opr>Ev Ib</opr>
- </def>
- </instruction>
-
- <instruction>
- <mnemonic>call</mnemonic>
- <def>
- <pfx>aso oso rexw rexr rexx rexb</pfx>
- <opc>ff /reg=2</opc>
- <opr>Ev</opr>
</del><ins>+ <opc>ff /reg=2 /m=64</opc>
+ <opr>Eq</opr>
</ins><span class="cx"> <mode>def64</mode>
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>ff /reg=3</opc>
</span><del>- <opr>Ep</opr>
</del><ins>+ <opr>Fv</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="lines">@@ -457,9 +498,8 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso</pfx>
</span><del>- <opc>9a</opc>
- <opr>Ap</opr>
- <mode>inv64</mode>
</del><ins>+ <opc>9a /m=!64</opc>
+ <opr>Av</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -712,7 +752,7 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexw</pfx>
</span><span class="cx"> <opc>3d</opc>
</span><del>- <opr>rAX Iz</opr>
</del><ins>+ <opr>rAX sIz</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -721,43 +761,46 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>82 /reg=7</opc>
</del><ins>+ <opc>82 /reg=7 /m=!64</opc>
</ins><span class="cx"> <opr>Eb Ib</opr>
</span><span class="cx"> <mode>inv64</mode>
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>81 /reg=7</opc>
</span><del>- <opr>Ev Iz</opr>
</del><ins>+ <opr>Ev sIz</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>83 /reg=7</opc>
</span><del>- <opr>Ev Ib</opr>
</del><ins>+ <opr>Ev sIb</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>cmppd</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f c2</opc>
- <opr>V W Ib</opr>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f c2</opc>
+ <opr>V H W Ib</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>cmpps</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
</ins><span class="cx"> <opc>0f c2</opc>
</span><del>- <opr>V W Ib</opr>
</del><ins>+ <opr>V H W Ib</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>cmpsb</mnemonic>
</span><span class="cx"> <def>
</span><ins>+ <pfx>repz seg</pfx>
</ins><span class="cx"> <opc>a6</opc>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -765,7 +808,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>cmpsw</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>oso rexw</pfx>
</del><ins>+ <pfx>repz oso rexw seg</pfx>
</ins><span class="cx"> <opc>a7 /o=16</opc>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -773,20 +816,21 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>cmpsd</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>oso rexw</pfx>
</del><ins>+ <pfx>repz oso rexw seg</pfx>
</ins><span class="cx"> <opc>a7 /o=32</opc>
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>ssef2 0f c2</opc>
- <opr>V W Ib</opr>
</del><ins>+ <opc>/sse=f2 0f c2</opc>
+ <opr>V H W Ib</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>cmpsq</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>oso rexw</pfx>
</del><ins>+ <pfx>repz oso rexw seg</pfx>
</ins><span class="cx"> <opc>a7 /o=64</opc>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -795,8 +839,9 @@
</span><span class="cx"> <mnemonic>cmpss</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>ssef3 0f c2</opc>
- <opr>V W Ib</opr>
</del><ins>+ <opc>/sse=f3 0f c2</opc>
+ <opr>V H W Ib</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -818,17 +863,32 @@
</span><span class="cx"> <mnemonic>cmpxchg8b</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>0f c7 /reg=1</opc>
</del><ins>+ <opc>0f c7 /mod=!11 /reg=1 /o=16</opc>
</ins><span class="cx"> <opr>M</opr>
</span><span class="cx"> </def>
</span><ins>+ <def>
+ <pfx>aso rexr rexx rexb</pfx>
+ <opc>0f c7 /mod=!11 /reg=1 /o=32</opc>
+ <opr>M</opr>
+ </def>
</ins><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><ins>+ <mnemonic>cmpxchg16b</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb</pfx>
+ <opc>0f c7 /mod=!11 /reg=1 /o=64</opc>
+ <opr>M</opr>
+ </def>
+ </instruction>
+
+ <instruction>
</ins><span class="cx"> <mnemonic>comisd</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 2f</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 2f</opc>
+ <opr>Vsd Wsd</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -838,6 +898,7 @@
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>0f 2f</opc>
</span><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -851,9 +912,10 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>cvtdq2pd</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>ssef3 0f e6</opc>
- <opr>V W</opr>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=f3 0f e6</opc>
+ <opr>V Wdq</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -863,15 +925,17 @@
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>0f 5b</opc>
</span><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>cvtpd2dq</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>ssef2 0f e6</opc>
- <opr>V W</opr>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=f2 0f e6</opc>
+ <opr>Vdq W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -879,7 +943,7 @@
</span><span class="cx"> <mnemonic>cvtpd2pi</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 2d</opc>
</del><ins>+ <opc>/sse=66 0f 2d</opc>
</ins><span class="cx"> <opr>P W</opr>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -887,9 +951,10 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>cvtpd2ps</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 5a</opc>
- <opr>V W</opr>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 5a</opc>
+ <opr>Vdq W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -906,7 +971,7 @@
</span><span class="cx"> <mnemonic>cvtpi2pd</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 2a</opc>
</del><ins>+ <opc>/sse=66 0f 2a</opc>
</ins><span class="cx"> <opr>V Q</opr>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -914,27 +979,29 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>cvtps2dq</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 5b</opc>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 5b</opc>
</ins><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><del>- <mnemonic>cvtps2pi</mnemonic>
</del><ins>+ <mnemonic>cvtps2pd</mnemonic>
</ins><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>0f 2d</opc>
- <opr>P W</opr>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>0f 5a</opc>
+ <opr>V Wdq</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><del>- <mnemonic>cvtps2pd</mnemonic>
</del><ins>+ <mnemonic>cvtps2pi</mnemonic>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>0f 5a</opc>
- <opr>V W</opr>
</del><ins>+ <opc>0f 2d</opc>
+ <opr>P MqU</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -942,8 +1009,9 @@
</span><span class="cx"> <mnemonic>cvtsd2si</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexw rexr rexx rexb</pfx>
</span><del>- <opc>ssef2 0f 2d</opc>
- <opr>Gy W</opr>
</del><ins>+ <opc>/sse=f2 0f 2d</opc>
+ <opr>Gy MqU</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -951,26 +1019,29 @@
</span><span class="cx"> <mnemonic>cvtsd2ss</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>ssef2 0f 5a</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=f2 0f 5a</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><del>- <mnemonic>cvtsi2ss</mnemonic>
</del><ins>+ <mnemonic>cvtsi2sd</mnemonic>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexw rexr rexx rexb</pfx>
</span><del>- <opc>ssef3 0f 2a</opc>
- <opr>V Ex</opr>
</del><ins>+ <opc>/sse=f2 0f 2a</opc>
+ <opr>V H Ey</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><del>- <mnemonic>cvtss2si</mnemonic>
</del><ins>+ <mnemonic>cvtsi2ss</mnemonic>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexw rexr rexx rexb</pfx>
</span><del>- <opc>ssef3 0f 2d</opc>
- <opr>Gy W</opr>
</del><ins>+ <opc>/sse=f3 0f 2a</opc>
+ <opr>V H Ey</opr>
+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -978,35 +1049,48 @@
</span><span class="cx"> <mnemonic>cvtss2sd</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>ssef3 0f 5a</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=f3 0f 5a</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><del>- <mnemonic>cvttpd2pi</mnemonic>
</del><ins>+ <mnemonic>cvtss2si</mnemonic>
</ins><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 2c</opc>
- <opr>P W</opr>
</del><ins>+ <pfx>aso rexw rexr rexx rexb</pfx>
+ <opc>/sse=f3 0f 2d</opc>
+ <opr>Gy MdU</opr>
+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>cvttpd2dq</mnemonic>
</span><span class="cx"> <def>
</span><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f e6</opc>
+ <opr>Vdq W</opr>
+ <cpuid>sse2 avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>cvttpd2pi</mnemonic>
+ <def>
</ins><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f e6</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 2c</opc>
+ <opr>P W</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>cvttps2dq</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>ssef3 0f 5b</opc>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=f3 0f 5b</opc>
</ins><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -1023,26 +1107,19 @@
</span><span class="cx"> <mnemonic>cvttsd2si</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexw rexr rexx rexb</pfx>
</span><del>- <opc>ssef2 0f 2c</opc>
- <opr>Gy Wsd</opr>
</del><ins>+ <opc>/sse=f2 0f 2c</opc>
+ <opr>Gy MqU</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><del>- <mnemonic>cvtsi2sd</mnemonic>
- <def>
- <pfx>aso rexw rexr rexx rexb</pfx>
- <opc>ssef2 0f 2a</opc>
- <opr>V Ex</opr>
- </def>
- </instruction>
-
- <instruction>
</del><span class="cx"> <mnemonic>cvttss2si</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexw rexr rexx rexb</pfx>
</span><del>- <opc>ssef3 0f 2c</opc>
- <opr>Gy Wsd</opr>
</del><ins>+ <opc>/sse=f3 0f 2c</opc>
+ <opr>Gy MdU</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -1073,7 +1150,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>daa</mnemonic>
</span><span class="cx"> <def>
</span><del>- <opc>27</opc>
</del><ins>+ <opc>27 /m=!64</opc>
</ins><span class="cx"> <mode>inv64</mode>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -1081,7 +1158,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>das</mnemonic>
</span><span class="cx"> <def>
</span><del>- <opc>2f</opc>
</del><ins>+ <opc>2f /m=!64</opc>
</ins><span class="cx"> <mode>inv64</mode>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -1091,42 +1168,42 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>48</opc>
</span><del>- <opr>eAX</opr>
</del><ins>+ <opr>R0z</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>49</opc>
</span><del>- <opr>eCX</opr>
</del><ins>+ <opr>R1z</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>4a</opc>
</span><del>- <opr>eDX</opr>
</del><ins>+ <opr>R2z</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>4b</opc>
</span><del>- <opr>eBX</opr>
</del><ins>+ <opr>R3z</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>4c</opc>
</span><del>- <opr>eSP</opr>
</del><ins>+ <opr>R4z</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>4d</opc>
</span><del>- <opr>eBP</opr>
</del><ins>+ <opr>R5z</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>4e</opc>
</span><del>- <opr>eSI</opr>
</del><ins>+ <opr>R6z</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>4f</opc>
</span><del>- <opr>eDI</opr>
</del><ins>+ <opr>R7z</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexw rexr rexx rexb</pfx>
</span><span class="lines">@@ -1157,9 +1234,10 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>divpd</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 5e</opc>
- <opr>V W</opr>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 5e</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -1168,7 +1246,8 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>0f 5e</opc>
</span><del>- <opr>V W</opr>
</del><ins>+ <opr>V H W</opr>
+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -1176,8 +1255,9 @@
</span><span class="cx"> <mnemonic>divsd</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>ssef2 0f 5e</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=f2 0f 5e</opc>
+ <opr>V H MqU</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -1185,12 +1265,33 @@
</span><span class="cx"> <mnemonic>divss</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>ssef3 0f 5e</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=f3 0f 5e</opc>
+ <opr>V H MdU</opr>
+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><ins>+ <mnemonic>dppd</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb</pfx>
+ <opc>/sse=66 0f 3a 41</opc>
+ <opr>V H W Ib</opr>
+ <cpuid>sse4.1 avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>dpps</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 3a 40</opc>
+ <opr>V H W Ib</opr>
+ <cpuid>sse4.1 avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
</ins><span class="cx"> <mnemonic>emms</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <opc>0f 77</opc>
</span><span class="lines">@@ -1202,13 +1303,23 @@
</span><span class="cx"> <def>
</span><span class="cx"> <opc>c8</opc>
</span><span class="cx"> <opr>Iw Ib</opr>
</span><del>- <mode>def64 depM</mode>
</del><ins>+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><ins>+ <mnemonic>extractps</mnemonic>
+ <def>
+ <pfx>aso rexr rexw rexx rexb</pfx>
+ <opc>/sse=66 0f 3a 17</opc>
+ <opr>MdRy V Ib</opr>
+ <cpuid>sse4.1 avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
</ins><span class="cx"> <mnemonic>f2xm1</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>d9 /mod=11 /x87=30</opc>
</span><span class="cx"> </def>
</span><span class="lines">@@ -1216,7 +1327,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fabs</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>d9 /mod=11 /x87=21</opc>
</span><span class="cx"> </def>
</span><span class="lines">@@ -1224,7 +1335,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fadd</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>dc /mod=!11 /reg=0</opc>
</span><span class="lines">@@ -1303,7 +1414,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>faddp</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>de /mod=11 /x87=00</opc>
</span><span class="cx"> <opr>ST0 ST0</opr>
</span><span class="lines">@@ -1340,7 +1451,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fbld</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>df /mod=!11 /reg=4</opc>
</span><span class="lines">@@ -1350,7 +1461,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fbstp</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>df /mod=!11 /reg=6</opc>
</span><span class="lines">@@ -1360,7 +1471,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fchs</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>d9 /mod=11 /x87=20</opc>
</span><span class="cx"> </def>
</span><span class="lines">@@ -1368,7 +1479,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fclex</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>db /mod=11 /x87=22</opc>
</span><span class="cx"> </def>
</span><span class="lines">@@ -1376,7 +1487,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fcmovb</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>da /mod=11 /x87=00</opc>
</span><span class="cx"> <opr>ST0 ST0</opr>
</span><span class="lines">@@ -1413,7 +1524,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fcmove</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>da /mod=11 /x87=08</opc>
</span><span class="cx"> <opr>ST0 ST0</opr>
</span><span class="lines">@@ -1450,7 +1561,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fcmovbe</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>da /mod=11 /x87=10</opc>
</span><span class="cx"> <opr>ST0 ST0</opr>
</span><span class="lines">@@ -1487,7 +1598,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fcmovu</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>da /mod=11 /x87=18</opc>
</span><span class="cx"> <opr>ST0 ST0</opr>
</span><span class="lines">@@ -1524,7 +1635,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fcmovnb</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>db /mod=11 /x87=00</opc>
</span><span class="cx"> <opr>ST0 ST0</opr>
</span><span class="lines">@@ -1561,7 +1672,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fcmovne</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>db /mod=11 /x87=08</opc>
</span><span class="cx"> <opr>ST0 ST0</opr>
</span><span class="lines">@@ -1598,7 +1709,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fcmovnbe</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>db /mod=11 /x87=10</opc>
</span><span class="cx"> <opr>ST0 ST0</opr>
</span><span class="lines">@@ -1635,7 +1746,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fcmovnu</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>db /mod=11 /x87=18</opc>
</span><span class="cx"> <opr>ST0 ST0</opr>
</span><span class="lines">@@ -1672,7 +1783,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fucomi</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>db /mod=11 /x87=28</opc>
</span><span class="cx"> <opr>ST0 ST0</opr>
</span><span class="lines">@@ -1709,7 +1820,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fcom</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>d8 /mod=!11 /reg=2</opc>
</span><span class="lines">@@ -1756,7 +1867,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fcom2</mnemonic>
</span><del>- <class>X87 UNDOC</class>
</del><ins>+ <cpuid>X87 UNDOC</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>dc /mod=11 /x87=10</opc>
</span><span class="cx"> <opr>ST0</opr>
</span><span class="lines">@@ -1793,7 +1904,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fcomp3</mnemonic>
</span><del>- <class>X87 UNDOC</class>
</del><ins>+ <cpuid>X87 UNDOC</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>dc /mod=11 /x87=18</opc>
</span><span class="cx"> <opr>ST0</opr>
</span><span class="lines">@@ -1830,7 +1941,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fcomi</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>db /mod=11 /x87=30</opc>
</span><span class="cx"> <opr>ST0 ST0</opr>
</span><span class="lines">@@ -1867,7 +1978,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fucomip</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>df /mod=11 /x87=28</opc>
</span><span class="cx"> <opr>ST0 ST0</opr>
</span><span class="lines">@@ -1904,7 +2015,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fcomip</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>df /mod=11 /x87=30</opc>
</span><span class="cx"> <opr>ST0 ST0</opr>
</span><span class="lines">@@ -1941,7 +2052,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fcomp</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>d8 /mod=!11 /reg=3</opc>
</span><span class="lines">@@ -1988,7 +2099,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fcomp5</mnemonic>
</span><del>- <class>X87 UNDOC</class>
</del><ins>+ <cpuid>X87 UNDOC</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>de /mod=11 /x87=10</opc>
</span><span class="cx"> <opr>ST0</opr>
</span><span class="lines">@@ -2025,7 +2136,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fcompp</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>de /mod=11 /x87=19</opc>
</span><span class="cx"> </def>
</span><span class="lines">@@ -2033,7 +2144,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fcos</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>d9 /mod=11 /x87=3f</opc>
</span><span class="cx"> </def>
</span><span class="lines">@@ -2041,7 +2152,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fdecstp</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>d9 /mod=11 /x87=36</opc>
</span><span class="cx"> </def>
</span><span class="lines">@@ -2049,7 +2160,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fdiv</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>dc /mod=!11 /reg=6</opc>
</span><span class="lines">@@ -2128,7 +2239,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fdivp</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>de /mod=11 /x87=38</opc>
</span><span class="cx"> <opr>ST0 ST0</opr>
</span><span class="lines">@@ -2165,7 +2276,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fdivr</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>dc /mod=!11 /reg=7</opc>
</span><span class="lines">@@ -2244,7 +2355,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fdivrp</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>de /mod=11 /x87=30</opc>
</span><span class="cx"> <opr>ST0 ST0</opr>
</span><span class="lines">@@ -2288,7 +2399,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>ffree</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>dd /mod=11 /x87=00</opc>
</span><span class="cx"> <opr>ST0</opr>
</span><span class="lines">@@ -2325,7 +2436,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>ffreep</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>df /mod=11 /x87=00</opc>
</span><span class="cx"> <opr>ST0</opr>
</span><span class="lines">@@ -2362,7 +2473,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>ficom</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>de /mod=!11 /reg=2</opc>
</span><span class="lines">@@ -2377,7 +2488,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>ficomp</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>de /mod=!11 /reg=3</opc>
</span><span class="lines">@@ -2392,7 +2503,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fild</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>df /mod=!11 /reg=0</opc>
</span><span class="lines">@@ -2411,8 +2522,8 @@
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><del>- <mnemonic>fncstp</mnemonic>
- <class>X87</class>
</del><ins>+ <mnemonic>fincstp</mnemonic>
+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>d9 /mod=11 /x87=37</opc>
</span><span class="cx"> </def>
</span><span class="lines">@@ -2420,7 +2531,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fninit</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>db /mod=11 /x87=23</opc>
</span><span class="cx"> </def>
</span><span class="lines">@@ -2428,7 +2539,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fiadd</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>da /mod=!11 /reg=0</opc>
</span><span class="lines">@@ -2443,7 +2554,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fidivr</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>da /mod=!11 /reg=7</opc>
</span><span class="lines">@@ -2458,7 +2569,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fidiv</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>da /mod=!11 /reg=6</opc>
</span><span class="lines">@@ -2473,7 +2584,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fisub</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>da /mod=!11 /reg=4</opc>
</span><span class="lines">@@ -2488,7 +2599,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fisubr</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>da /mod=!11 /reg=5</opc>
</span><span class="lines">@@ -2503,7 +2614,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fist</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>df /mod=!11 /reg=2</opc>
</span><span class="lines">@@ -2518,7 +2629,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fistp</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>df /mod=!11 /reg=3</opc>
</span><span class="lines">@@ -2538,7 +2649,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fisttp</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>db /mod=!11 /reg=1</opc>
</span><span class="lines">@@ -2558,7 +2669,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fld</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>db /mod=!11 /reg=5</opc>
</span><span class="lines">@@ -2610,7 +2721,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fld1</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>d9 /mod=11 /x87=28</opc>
</span><span class="cx"> </def>
</span><span class="lines">@@ -2618,7 +2729,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fldl2t</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>d9 /mod=11 /x87=29</opc>
</span><span class="cx"> </def>
</span><span class="lines">@@ -2626,15 +2737,15 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fldl2e</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>d9 /mod=11 /x87=2a</opc>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><del>- <mnemonic>fldlpi</mnemonic>
- <class>X87</class>
</del><ins>+ <mnemonic>fldpi</mnemonic>
+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>d9 /mod=11 /x87=2b</opc>
</span><span class="cx"> </def>
</span><span class="lines">@@ -2642,7 +2753,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fldlg2</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>d9 /mod=11 /x87=2c</opc>
</span><span class="cx"> </def>
</span><span class="lines">@@ -2650,7 +2761,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fldln2</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>d9 /mod=11 /x87=2d</opc>
</span><span class="cx"> </def>
</span><span class="lines">@@ -2658,7 +2769,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fldz</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>d9 /mod=11 /x87=2e</opc>
</span><span class="cx"> </def>
</span><span class="lines">@@ -2666,7 +2777,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fldcw</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>d9 /mod=!11 /reg=5</opc>
</span><span class="lines">@@ -2676,7 +2787,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fldenv</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>d9 /mod=!11 /reg=4</opc>
</span><span class="lines">@@ -2686,7 +2797,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fmul</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>dc /mod=!11 /reg=1</opc>
</span><span class="lines">@@ -2765,7 +2876,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fmulp</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>de /mod=11 /x87=08</opc>
</span><span class="cx"> <opr>ST0 ST0</opr>
</span><span class="lines">@@ -2802,7 +2913,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fimul</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>da /mod=!11 /reg=1</opc>
</span><span class="lines">@@ -2817,15 +2928,39 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fnop</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>d9 /mod=11 /x87=10</opc>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><ins>+
+ <instruction>
+ <mnemonic>fndisi</mnemonic>
+ <cpuid>X87</cpuid>
+ <def>
+ <opc>db /mod=11 /x87=21</opc>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>fneni</mnemonic>
+ <cpuid>X87</cpuid>
+ <def>
+ <opc>db /mod=11 /x87=20</opc>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>fnsetpm</mnemonic>
+ <cpuid>X87</cpuid>
+ <def>
+ <opc>db /mod=11 /x87=24</opc>
+ </def>
+ </instruction>
</ins><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fpatan</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>d9 /mod=11 /x87=33</opc>
</span><span class="cx"> </def>
</span><span class="lines">@@ -2833,7 +2968,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fprem</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>d9 /mod=11 /x87=38</opc>
</span><span class="cx"> </def>
</span><span class="lines">@@ -2841,7 +2976,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fprem1</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>d9 /mod=11 /x87=35</opc>
</span><span class="cx"> </def>
</span><span class="lines">@@ -2849,7 +2984,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fptan</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>d9 /mod=11 /x87=32</opc>
</span><span class="cx"> </def>
</span><span class="lines">@@ -2857,7 +2992,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>frndint</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>d9 /mod=11 /x87=3c</opc>
</span><span class="cx"> </def>
</span><span class="lines">@@ -2865,17 +3000,25 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>frstor</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>dd /mod=!11 /reg=4</opc>
</span><span class="cx"> <opr>M</opr>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><ins>+
+ <instruction>
+ <mnemonic>frstpm</mnemonic>
+ <cpuid>X87</cpuid>
+ <def>
+ <opc>db /mod=11 /x87=25</opc>
+ </def>
+ </instruction>
</ins><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fnsave</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>dd /mod=!11 /reg=6</opc>
</span><span class="lines">@@ -2885,7 +3028,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fscale</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>d9 /mod=11 /x87=3d</opc>
</span><span class="cx"> </def>
</span><span class="lines">@@ -2893,7 +3036,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fsin</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>d9 /mod=11 /x87=3e</opc>
</span><span class="cx"> </def>
</span><span class="lines">@@ -2901,7 +3044,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fsincos</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>d9 /mod=11 /x87=3b</opc>
</span><span class="cx"> </def>
</span><span class="lines">@@ -2909,7 +3052,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fsqrt</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>d9 /mod=11 /x87=3a</opc>
</span><span class="cx"> </def>
</span><span class="lines">@@ -2917,7 +3060,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fstp</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>db /mod=!11 /reg=7</opc>
</span><span class="lines">@@ -3077,7 +3220,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fst</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>d9 /mod=!11 /reg=2</opc>
</span><span class="lines">@@ -3124,7 +3267,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fnstcw</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>d9 /mod=!11 /reg=7</opc>
</span><span class="lines">@@ -3134,7 +3277,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fnstenv</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>d9 /mod=!11 /reg=6</opc>
</span><span class="lines">@@ -3144,7 +3287,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fnstsw</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>dd /mod=!11 /reg=7</opc>
</span><span class="lines">@@ -3158,7 +3301,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fsub</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>d8 /mod=!11 /reg=4</opc>
</span><span class="lines">@@ -3237,7 +3380,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fsubp</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>de /mod=11 /x87=28</opc>
</span><span class="cx"> <opr>ST0 ST0</opr>
</span><span class="lines">@@ -3274,7 +3417,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fsubr</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>dc /mod=!11 /reg=5</opc>
</span><span class="lines">@@ -3353,7 +3496,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fsubrp</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>de /mod=11 /x87=20</opc>
</span><span class="cx"> <opr>ST0 ST0</opr>
</span><span class="lines">@@ -3390,7 +3533,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>ftst</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>d9 /mod=11 /x87=24</opc>
</span><span class="cx"> </def>
</span><span class="lines">@@ -3398,7 +3541,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fucom</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>dd /mod=11 /x87=20</opc>
</span><span class="cx"> <opr>ST0</opr>
</span><span class="lines">@@ -3435,7 +3578,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fucomp</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>dd /mod=11 /x87=28</opc>
</span><span class="cx"> <opr>ST0</opr>
</span><span class="lines">@@ -3472,7 +3615,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fucompp</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>da /mod=11 /x87=29</opc>
</span><span class="cx"> </def>
</span><span class="lines">@@ -3480,7 +3623,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fxam</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>d9 /mod=11 /x87=25</opc>
</span><span class="cx"> </def>
</span><span class="lines">@@ -3488,7 +3631,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fxch</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>d9 /mod=11 /x87=08</opc>
</span><span class="cx"> <opr>ST0 ST0</opr>
</span><span class="lines">@@ -3525,7 +3668,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fxch4</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>dd /mod=11 /x87=08</opc>
</span><span class="cx"> <opr>ST0</opr>
</span><span class="lines">@@ -3562,7 +3705,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fxch7</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>df /mod=11 /x87=08</opc>
</span><span class="cx"> <opr>ST0</opr>
</span><span class="lines">@@ -3601,7 +3744,7 @@
</span><span class="cx"> <mnemonic>fxrstor</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexw rexr rexx rexb</pfx>
</span><del>- <opc>0f ae /mod=11 /reg=1</opc>
</del><ins>+ <opc>0f ae /mod=!11 /reg=1</opc>
</ins><span class="cx"> <opr>M</opr>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -3610,14 +3753,14 @@
</span><span class="cx"> <mnemonic>fxsave</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexw rexr rexx rexb</pfx>
</span><del>- <opc>0f ae /mod=11 /reg=0</opc>
</del><ins>+ <opc>0f ae /mod=!11 /reg=0</opc>
</ins><span class="cx"> <opr>M</opr>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><del>- <mnemonic>fpxtract</mnemonic>
- <class>X87</class>
</del><ins>+ <mnemonic>fxtract</mnemonic>
+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>d9 /mod=11 /x87=34</opc>
</span><span class="cx"> </def>
</span><span class="lines">@@ -3625,7 +3768,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fyl2x</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>d9 /mod=11 /x87=31</opc>
</span><span class="cx"> </def>
</span><span class="lines">@@ -3633,7 +3776,7 @@
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>fyl2xp1</mnemonic>
</span><del>- <class>X87</class>
</del><ins>+ <cpuid>X87</cpuid>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>d9 /mod=11 /x87=39</opc>
</span><span class="cx"> </def>
</span><span class="lines">@@ -3703,13 +3846,11 @@
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>69</opc>
</span><span class="cx"> <opr>Gv Ev Iz</opr>
</span><del>- <syn>sext</syn>
</del><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>6b</opc>
</span><del>- <opr>Gv Ev Ib</opr>
- <syn>sext</syn>
</del><ins>+ <opr>Gv Ev sIb</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -3718,42 +3859,42 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>40</opc>
</span><del>- <opr>eAX</opr>
</del><ins>+ <opr>R0z</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>41</opc>
</span><del>- <opr>eCX</opr>
</del><ins>+ <opr>R1z</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>42</opc>
</span><del>- <opr>eDX</opr>
</del><ins>+ <opr>R2z</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>43</opc>
</span><del>- <opr>eBX</opr>
</del><ins>+ <opr>R3z</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>44</opc>
</span><del>- <opr>eSP</opr>
</del><ins>+ <opr>R4z</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>45</opc>
</span><del>- <opr>eBP</opr>
</del><ins>+ <opr>R5z</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>46</opc>
</span><del>- <opr>eSI</opr>
</del><ins>+ <opr>R6z</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>47</opc>
</span><del>- <opr>eDI</opr>
</del><ins>+ <opr>R7z</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="lines">@@ -3770,6 +3911,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>insb</mnemonic>
</span><span class="cx"> <def>
</span><ins>+ <pfx>rep seg</pfx>
</ins><span class="cx"> <opc>6c</opc>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -3777,7 +3919,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>insw</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>oso</pfx>
</del><ins>+ <pfx>rep oso seg</pfx>
</ins><span class="cx"> <opc>6d /o=16</opc>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -3785,7 +3927,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>insd</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>oso</pfx>
</del><ins>+ <pfx>rep oso seg</pfx>
</ins><span class="cx"> <opc>6d /o=32</opc>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -3815,7 +3957,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>into</mnemonic>
</span><span class="cx"> <def>
</span><del>- <opc>ce</opc>
</del><ins>+ <opc>ce /m=!64</opc>
</ins><span class="cx"> <mode>inv64</mode>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -3831,11 +3973,11 @@
</span><span class="cx"> <mnemonic>invept</mnemonic>
</span><span class="cx"> <vendor>intel</vendor>
</span><span class="cx"> <def>
</span><del>- <opc>sse66 0f 38 80 /m=32</opc>
</del><ins>+ <opc>/sse=66 0f 38 80 /m=32</opc>
</ins><span class="cx"> <opr>Gd Mo</opr>
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <opc>sse66 0f 38 80 /m=64</opc>
</del><ins>+ <opc>/sse=66 0f 38 80 /m=64</opc>
</ins><span class="cx"> <opr>Gq Mo</opr>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -3861,11 +4003,11 @@
</span><span class="cx"> <mnemonic>invvpid</mnemonic>
</span><span class="cx"> <vendor>intel</vendor>
</span><span class="cx"> <def>
</span><del>- <opc>sse66 0f 38 81 /m=32</opc>
</del><ins>+ <opc>/sse=66 0f 38 81 /m=32</opc>
</ins><span class="cx"> <opr>Gd Mo</opr>
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <opc>sse66 0f 38 81 /m=64</opc>
</del><ins>+ <opc>/sse=66 0f 38 81 /m=64</opc>
</ins><span class="cx"> <opr>Gq Mo</opr>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -3904,7 +4046,7 @@
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>0f 80</opc>
</span><span class="cx"> <opr>Jz</opr>
</span><del>- <mode>def64 depM</mode>
</del><ins>+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -3918,7 +4060,7 @@
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>0f 81</opc>
</span><span class="cx"> <opr>Jz</opr>
</span><del>- <mode>def64 depM</mode>
</del><ins>+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -3932,7 +4074,7 @@
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>0f 82</opc>
</span><span class="cx"> <opr>Jz</opr>
</span><del>- <mode>def64 depM</mode>
</del><ins>+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -3946,7 +4088,7 @@
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>0f 83</opc>
</span><span class="cx"> <opr>Jz</opr>
</span><del>- <mode>def64 depM</mode>
</del><ins>+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -3960,7 +4102,7 @@
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>0f 84</opc>
</span><span class="cx"> <opr>Jz</opr>
</span><del>- <mode>def64 depM</mode>
</del><ins>+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -3974,7 +4116,7 @@
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>0f 85</opc>
</span><span class="cx"> <opr>Jz</opr>
</span><del>- <mode>def64 depM</mode>
</del><ins>+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -3988,7 +4130,7 @@
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>0f 86</opc>
</span><span class="cx"> <opr>Jz</opr>
</span><del>- <mode>def64 depM</mode>
</del><ins>+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -4002,7 +4144,7 @@
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>0f 87</opc>
</span><span class="cx"> <opr>Jz</opr>
</span><del>- <mode>def64 depM</mode>
</del><ins>+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -4016,7 +4158,7 @@
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>0f 88</opc>
</span><span class="cx"> <opr>Jz</opr>
</span><del>- <mode>def64 depM</mode>
</del><ins>+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -4030,7 +4172,7 @@
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>0f 89</opc>
</span><span class="cx"> <opr>Jz</opr>
</span><del>- <mode>def64 depM</mode>
</del><ins>+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -4044,7 +4186,7 @@
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>0f 8a</opc>
</span><span class="cx"> <opr>Jz</opr>
</span><del>- <mode>def64 depM</mode>
</del><ins>+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -4058,7 +4200,7 @@
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>0f 8b</opc>
</span><span class="cx"> <opr>Jz</opr>
</span><del>- <mode>def64 depM</mode>
</del><ins>+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -4072,7 +4214,7 @@
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>0f 8c</opc>
</span><span class="cx"> <opr>Jz</opr>
</span><del>- <mode>def64 depM</mode>
</del><ins>+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -4086,7 +4228,7 @@
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>0f 8d</opc>
</span><span class="cx"> <opr>Jz</opr>
</span><del>- <mode>def64 depM</mode>
</del><ins>+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -4100,7 +4242,7 @@
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>0f 8e</opc>
</span><span class="cx"> <opr>Jz</opr>
</span><del>- <mode>def64 depM</mode>
</del><ins>+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -4114,7 +4256,7 @@
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>0f 8f</opc>
</span><span class="cx"> <opr>Jz</opr>
</span><del>- <mode>def64 depM</mode>
</del><ins>+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -4151,28 +4293,28 @@
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>ff /reg=4</opc>
</span><span class="cx"> <opr>Ev</opr>
</span><del>- <mode>def64 depM</mode>
</del><ins>+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>ff /reg=5</opc>
</span><del>- <opr>Ep</opr>
</del><ins>+ <opr>Fv</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>e9</opc>
</span><span class="cx"> <opr>Jz</opr>
</span><del>- <mode>def64 depM</mode>
- <syn>cast</syn>
</del><ins>+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <opc>ea</opc>
- <opr>Ap</opr>
- <mode>inv64</mode>
</del><ins>+ <pfx>oso</pfx>
+ <opc>ea /m=!64</opc>
+ <opr>Av</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <opc>eb</opc>
</span><span class="cx"> <opr>Jb</opr>
</span><ins>+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -4193,19 +4335,10 @@
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><del>- <mnemonic>lddqu</mnemonic>
- <def>
- <pfx>aso rexr rexx rexb</pfx>
- <opc>ssef2 0f f0</opc>
- <opr>V M</opr>
- </def>
- </instruction>
-
- <instruction>
</del><span class="cx"> <mnemonic>ldmxcsr</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexw rexr rexx rexb</pfx>
</span><del>- <opc>0f ae /reg=2 /mod=11</opc>
</del><ins>+ <opc>0f ae /reg=2 /mod=!11</opc>
</ins><span class="cx"> <opr>Md</opr>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -4214,9 +4347,8 @@
</span><span class="cx"> <mnemonic>lds</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso</pfx>
</span><del>- <opc>c5</opc>
</del><ins>+ <opc>c5 /vex=none /m=!64</opc>
</ins><span class="cx"> <opr>Gv M</opr>
</span><del>- <mode>inv64</mode>
</del><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -4233,9 +4365,8 @@
</span><span class="cx"> <mnemonic>les</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso</pfx>
</span><del>- <opc>c4</opc>
</del><ins>+ <opc>c4 /m=!64</opc>
</ins><span class="cx"> <opr>Gv M</opr>
</span><del>- <mode>inv64</mode>
</del><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -4271,7 +4402,7 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>0f b2</opc>
</span><del>- <opr>Gz M</opr>
</del><ins>+ <opr>Gv M</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -4335,6 +4466,11 @@
</span><span class="cx"> <opc>0f 01 /reg=6 /mod=!11</opc>
</span><span class="cx"> <opr>Ew</opr>
</span><span class="cx"> </def>
</span><ins>+ <def>
+ <pfx>aso rexr rexx rexb</pfx>
+ <opc>0f 01 /reg=6 /mod=11</opc>
+ <opr>Ew</opr>
+ </def>
</ins><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="lines">@@ -4347,7 +4483,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>lodsb</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>seg</pfx>
</del><ins>+ <pfx>rep seg</pfx>
</ins><span class="cx"> <opc>ac</opc>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -4355,7 +4491,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>lodsw</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>seg oso rexw</pfx>
</del><ins>+ <pfx>rep seg oso rexw</pfx>
</ins><span class="cx"> <opc>ad /o=16</opc>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -4363,7 +4499,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>lodsd</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>seg oso rexw</pfx>
</del><ins>+ <pfx>rep seg oso rexw</pfx>
</ins><span class="cx"> <opc>ad /o=32</opc>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -4371,13 +4507,13 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>lodsq</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>seg oso rexw</pfx>
</del><ins>+ <pfx>rep seg oso rexw</pfx>
</ins><span class="cx"> <opc>ad /o=64</opc>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><del>- <mnemonic>loopnz</mnemonic>
</del><ins>+ <mnemonic>loopne</mnemonic>
</ins><span class="cx"> <def>
</span><span class="cx"> <opc>e0</opc>
</span><span class="cx"> <opr>Jb</opr>
</span><span class="lines">@@ -4422,26 +4558,28 @@
</span><span class="cx"> <mnemonic>maskmovq</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>0f f7</opc>
- <opr>P PR</opr>
</del><ins>+ <opc>0f f7 /mod=11</opc>
+ <opr>P N</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>maxpd</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 5f</opc>
- <opr>V W</opr>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 5f</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>maxps</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
</ins><span class="cx"> <opc>0f 5f</opc>
</span><del>- <opr>V W</opr>
</del><ins>+ <opr>V H W</opr>
+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -4449,8 +4587,9 @@
</span><span class="cx"> <mnemonic>maxsd</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>ssef2 0f 5f</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=f2 0f 5f</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -4458,8 +4597,9 @@
</span><span class="cx"> <mnemonic>maxss</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>ssef3 0f 5f</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=f3 0f 5f</opc>
+ <opr>V H W</opr>
+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -4494,9 +4634,10 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>minpd</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 5d</opc>
- <opr>V W</opr>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 5d</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -4505,7 +4646,8 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>0f 5d</opc>
</span><del>- <opr>V W</opr>
</del><ins>+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -4513,8 +4655,9 @@
</span><span class="cx"> <mnemonic>minsd</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>ssef2 0f 5d</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=f2 0f 5d</opc>
+ <opr>V H MqU</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -4522,8 +4665,9 @@
</span><span class="cx"> <mnemonic>minss</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>ssef3 0f 5d</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=f3 0f 5d</opc>
+ <opr>V H MdU</opr>
+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -4551,7 +4695,7 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>c7 /reg=0</opc>
</span><del>- <opr>Ev Iz</opr>
</del><ins>+ <opr>Ev sIz</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -4574,14 +4718,14 @@
</span><span class="cx"> <opr>Gv Ev</opr>
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <pfx>aso oso rexr rexx rexb</pfx>
</del><ins>+ <pfx>aso oso rexw rexr rexx rexb</pfx>
</ins><span class="cx"> <opc>8c</opc>
</span><del>- <opr>Ev S</opr>
</del><ins>+ <opr>MwRv S</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <pfx>aso oso rexr rexx rexb</pfx>
</del><ins>+ <pfx>aso oso rexw rexr rexx rexb</pfx>
</ins><span class="cx"> <opc>8e</opc>
</span><del>- <opr>S Ev</opr>
</del><ins>+ <opr>S MwRv</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <opc>a0</opc>
</span><span class="lines">@@ -4604,100 +4748,100 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>rexb</pfx>
</span><span class="cx"> <opc>b0</opc>
</span><del>- <opr>ALr8b Ib</opr>
</del><ins>+ <opr>R0b Ib</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>rexb</pfx>
</span><span class="cx"> <opc>b1</opc>
</span><del>- <opr>CLr9b Ib</opr>
</del><ins>+ <opr>R1b Ib</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>rexb</pfx>
</span><span class="cx"> <opc>b2</opc>
</span><del>- <opr>DLr10b Ib</opr>
</del><ins>+ <opr>R2b Ib</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>rexb</pfx>
</span><span class="cx"> <opc>b3</opc>
</span><del>- <opr>BLr11b Ib</opr>
</del><ins>+ <opr>R3b Ib</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>rexb</pfx>
</span><span class="cx"> <opc>b4</opc>
</span><del>- <opr>AHr12b Ib</opr>
</del><ins>+ <opr>R4b Ib</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>rexb</pfx>
</span><span class="cx"> <opc>b5</opc>
</span><del>- <opr>CHr13b Ib</opr>
</del><ins>+ <opr>R5b Ib</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>rexb</pfx>
</span><span class="cx"> <opc>b6</opc>
</span><del>- <opr>DHr14b Ib</opr>
</del><ins>+ <opr>R6b Ib</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>rexb</pfx>
</span><span class="cx"> <opc>b7</opc>
</span><del>- <opr>BHr15b Ib</opr>
</del><ins>+ <opr>R7b Ib</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexw rexb</pfx>
</span><span class="cx"> <opc>b8</opc>
</span><del>- <opr>rAXr8 Iv</opr>
</del><ins>+ <opr>R0v Iv</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexw rexb</pfx>
</span><span class="cx"> <opc>b9</opc>
</span><del>- <opr>rCXr9 Iv</opr>
</del><ins>+ <opr>R1v Iv</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexw rexb</pfx>
</span><span class="cx"> <opc>ba</opc>
</span><del>- <opr>rDXr10 Iv</opr>
</del><ins>+ <opr>R2v Iv</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexw rexb</pfx>
</span><span class="cx"> <opc>bb</opc>
</span><del>- <opr>rBXr11 Iv</opr>
</del><ins>+ <opr>R3v Iv</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexw rexb</pfx>
</span><span class="cx"> <opc>bc</opc>
</span><del>- <opr>rSPr12 Iv</opr>
</del><ins>+ <opr>R4v Iv</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexw rexb</pfx>
</span><span class="cx"> <opc>bd</opc>
</span><del>- <opr>rBPr13 Iv</opr>
</del><ins>+ <opr>R5v Iv</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexw rexb</pfx>
</span><span class="cx"> <opc>be</opc>
</span><del>- <opr>rSIr14 Iv</opr>
</del><ins>+ <opr>R6v Iv</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexw rexb</pfx>
</span><span class="cx"> <opc>bf</opc>
</span><del>- <opr>rDIr15 Iv</opr>
</del><ins>+ <opr>R7v Iv</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <pfx>rexr</pfx>
</del><ins>+ <pfx>rexr rexw rexb</pfx>
</ins><span class="cx"> <opc>0f 20</opc>
</span><span class="cx"> <opr>R C</opr>
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <pfx>rexr</pfx>
</del><ins>+ <pfx>rexr rexw rexb</pfx>
</ins><span class="cx"> <opc>0f 21</opc>
</span><span class="cx"> <opr>R D</opr>
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <pfx>rexr</pfx>
</del><ins>+ <pfx>rexr rexw rexb</pfx>
</ins><span class="cx"> <opc>0f 22</opc>
</span><span class="cx"> <opr>C R</opr>
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <pfx>rexr</pfx>
</del><ins>+ <pfx>rexr rexw rexb</pfx>
</ins><span class="cx"> <opc>0f 23</opc>
</span><span class="cx"> <opr>D R</opr>
</span><span class="cx"> </def>
</span><span class="lines">@@ -4706,28 +4850,32 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>movapd</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 28</opc>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 28</opc>
</ins><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 29</opc>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 29</opc>
</ins><span class="cx"> <opr>W V</opr>
</span><ins>+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>movaps</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
</ins><span class="cx"> <opc>0f 28</opc>
</span><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
</ins><span class="cx"> <opc>0f 29</opc>
</span><span class="cx"> <opr>W V</opr>
</span><ins>+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -4735,37 +4883,68 @@
</span><span class="cx"> <mnemonic>movd</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexw rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 6e</opc>
- <opr>V Ex</opr>
</del><ins>+ <opc>0f 6e /o=16</opc>
+ <opr>P Ey</opr>
+ <cpuid>mmx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>0f 6e</opc>
- <opr>P Ex</opr>
</del><ins>+ <pfx>aso rexw rexr rexx rexb</pfx>
+ <opc>0f 6e /o=32</opc>
+ <opr>P Ey</opr>
+ <cpuid>mmx</cpuid>
</ins><span class="cx"> </def>
</span><ins>+
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexw rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 7e</opc>
- <opr>Ex V</opr>
</del><ins>+ <opc>/sse=66 0f 6e /o=16</opc>
+ <opr>V Ey</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>0f 7e</opc>
- <opr>Ex P</opr>
</del><ins>+ <pfx>aso rexw rexr rexx rexb</pfx>
+ <opc>/sse=66 0f 6e /o=32</opc>
+ <opr>V Ey</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><ins>+ <def>
+ <pfx>aso rexw rexr rexx rexb</pfx>
+ <opc>0f 7e /o=16</opc>
+ <opr>Ey P</opr>
+ <cpuid>mmx</cpuid>
+ </def>
+ <def>
+ <pfx>aso rexw rexr rexx rexb</pfx>
+ <opc>0f 7e /o=32</opc>
+ <opr>Ey P</opr>
+ <cpuid>mmx</cpuid>
+ </def>
+ <def>
+ <pfx>aso rexw rexr rexx rexb</pfx>
+ <opc>/sse=66 0f 7e /o=16</opc>
+ <opr>Ey V</opr>
+ <cpuid>sse2 avx</cpuid>
+ </def>
+ <def>
+ <pfx>aso rexw rexr rexx rexb</pfx>
+ <opc>/sse=66 0f 7e /o=32</opc>
+ <opr>Ey V</opr>
+ <cpuid>sse2 avx</cpuid>
+ </def>
</ins><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>movhpd</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 16 /mod=!11</opc>
- <opr>V M</opr>
</del><ins>+ <opc>/sse=66 0f 16 /mod=!11</opc>
+ <opr>V H M</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 17</opc>
</del><ins>+ <opc>/sse=66 0f 17</opc>
</ins><span class="cx"> <opr>M V</opr>
</span><ins>+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -4774,12 +4953,14 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>0f 16 /mod=!11</opc>
</span><del>- <opr>V M</opr>
</del><ins>+ <opr>V H M</opr>
+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>0f 17</opc>
</span><span class="cx"> <opr>M V</opr>
</span><ins>+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -4788,7 +4969,8 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>0f 16 /mod=11</opc>
</span><del>- <opr>V VR</opr>
</del><ins>+ <opr>V H U</opr>
+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -4796,14 +4978,15 @@
</span><span class="cx"> <mnemonic>movlpd</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 12 /mod=!11</opc>
</del><ins>+ <opc>/sse=66 0f 12 /mod=!11</opc>
</ins><span class="cx"> <opr>V M</opr>
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 13</opc>
</del><ins>+ <opc>/sse=66 0f 13</opc>
</ins><span class="cx"> <opr>M V</opr>
</span><span class="cx"> </def>
</span><ins>+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="lines">@@ -4818,6 +5001,7 @@
</span><span class="cx"> <opc>0f 13</opc>
</span><span class="cx"> <opr>M V</opr>
</span><span class="cx"> </def>
</span><ins>+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="lines">@@ -4825,16 +5009,18 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>0f 12 /mod=11</opc>
</span><del>- <opr>V VR</opr>
</del><ins>+ <opr>V U</opr>
+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>movmskpd</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>oso rexr rexb</pfx>
- <opc>sse66 0f 50</opc>
- <opr>Gd VR</opr>
</del><ins>+ <pfx>oso rexr rexb vexl</pfx>
+ <opc>/sse=66 0f 50</opc>
+ <opr>Gd U</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -4843,16 +5029,18 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexr rexb</pfx>
</span><span class="cx"> <opc>0f 50</opc>
</span><del>- <opr>Gd VR</opr>
</del><ins>+ <opr>Gd U</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>movntdq</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f e7</opc>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f e7</opc>
</ins><span class="cx"> <opr>M V</opr>
</span><ins>+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -4868,24 +5056,27 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>movntpd</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 2b</opc>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 2b</opc>
</ins><span class="cx"> <opr>M V</opr>
</span><ins>+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>movntps</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
</ins><span class="cx"> <opc>0f 2b</opc>
</span><span class="cx"> <opr>M V</opr>
</span><ins>+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>movntq</mnemonic>
</span><span class="cx"> <def>
</span><ins>+ <pfx>aso rexr rexx rexb</pfx>
</ins><span class="cx"> <opc>0f e7</opc>
</span><span class="cx"> <opr>M P</opr>
</span><span class="cx"> </def>
</span><span class="lines">@@ -4894,31 +5085,59 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>movq</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>0f 6f</opc>
- <opr>P Q</opr>
</del><ins>+ <pfx>aso rexw rexr rexx rexb</pfx>
+ <opc>0f 6e /o=64</opc>
+ <opr>P Eq</opr>
+ <cpuid>mmx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f d6</opc>
- <opr>W V</opr>
</del><ins>+ <pfx>aso rexw rexr rexx rexb</pfx>
+ <opc>/sse=66 0f 6e /o=64</opc>
+ <opr>V Eq</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>ssef3 0f 7e</opc>
</del><ins>+ <pfx>aso rexw rexr rexx rexb</pfx>
+ <opc>0f 7e /o=64</opc>
+ <opr>Eq P</opr>
+ <cpuid>mmx</cpuid>
+ </def>
+ <def>
+ <pfx>aso rexw rexr rexx rexb</pfx>
+ <opc>/sse=66 0f 7e /o=64</opc>
+ <opr>Eq V</opr>
+ <cpuid>sse2 avx</cpuid>
+ </def>
+ <def>
+ <pfx>aso rexw rexr rexx rexb</pfx>
+ <opc>/sse=f3 0f 7e</opc>
</ins><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
</del><ins>+ <pfx>aso rexw rexr rexx rexb</pfx>
+ <opc>/sse=66 0f d6</opc>
+ <opr>W V</opr>
+ <cpuid>sse2 avx</cpuid>
+ </def>
+ <def>
+ <pfx>aso rexw rexr rexx rexb</pfx>
+ <opc>0f 6f</opc>
+ <opr>P Q</opr>
+ <cpuid>mmx</cpuid>
+ </def>
+ <def>
+ <pfx>aso rexw rexr rexx rexb</pfx>
</ins><span class="cx"> <opc>0f 7f</opc>
</span><span class="cx"> <opr>Q P</opr>
</span><ins>+ <cpuid>mmx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>movsb</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>seg</pfx>
</del><ins>+ <pfx>rep seg</pfx>
</ins><span class="cx"> <opc>a4</opc>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -4926,7 +5145,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>movsw</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>seg oso rexw</pfx>
</del><ins>+ <pfx>rep seg oso rexw</pfx>
</ins><span class="cx"> <opc>a5 /o=16</opc>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -4934,25 +5153,27 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>movsd</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>seg oso rexw</pfx>
</del><ins>+ <pfx>rep seg oso rexw</pfx>
</ins><span class="cx"> <opc>a5 /o=32</opc>
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>ssef2 0f 10</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=f2 0f 10</opc>
+ <opr>V MqU</opr>
+ <cpuid>sse2</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>ssef2 0f 11</opc>
</del><ins>+ <opc>/sse=f2 0f 11</opc>
</ins><span class="cx"> <opr>W V</opr>
</span><ins>+ <cpuid>sse2</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>movsq</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>seg oso rexw</pfx>
</del><ins>+ <pfx>rep seg oso rexw</pfx>
</ins><span class="cx"> <opc>a5 /o=64</opc>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -4961,13 +5182,15 @@
</span><span class="cx"> <mnemonic>movss</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>ssef3 0f 10</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=f3 0f 10</opc>
+ <opr>V MdU</opr>
+ <cpuid>sse</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>ssef3 0f 11</opc>
</del><ins>+ <opc>/sse=f3 0f 11</opc>
</ins><span class="cx"> <opr>W V</opr>
</span><ins>+ <cpuid>sse</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -4981,35 +5204,39 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>0f bf</opc>
</span><del>- <opr>Gv Ew</opr>
</del><ins>+ <opr>Gy Ew</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>movupd</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 10</opc>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 10</opc>
</ins><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 11</opc>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 11</opc>
</ins><span class="cx"> <opr>W V</opr>
</span><ins>+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>movups</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
</ins><span class="cx"> <opc>0f 10</opc>
</span><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
</ins><span class="cx"> <opc>0f 11</opc>
</span><span class="cx"> <opr>W V</opr>
</span><ins>+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -5023,7 +5250,7 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>0f b7</opc>
</span><del>- <opr>Gv Ew</opr>
</del><ins>+ <opr>Gy Ew</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -5044,18 +5271,20 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>mulpd</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 59</opc>
- <opr>V W</opr>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 59</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>mulps</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
</ins><span class="cx"> <opc>0f 59</opc>
</span><del>- <opr>V W</opr>
</del><ins>+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -5063,8 +5292,9 @@
</span><span class="cx"> <mnemonic>mulsd</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>ssef2 0f 59</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=f2 0f 59</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -5072,8 +5302,9 @@
</span><span class="cx"> <mnemonic>mulss</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>ssef3 0f 59</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=f3 0f 59</opc>
+ <opr>V H W</opr>
+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -5101,9 +5332,6 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>nop</mnemonic>
</span><span class="cx"> <def>
</span><del>- <opc>90</opc>
- </def>
- <def>
</del><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>0f 19</opc>
</span><span class="cx"> <opr>M</opr>
</span><span class="lines">@@ -5183,8 +5411,7 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexw</pfx>
</span><span class="cx"> <opc>0d</opc>
</span><del>- <opr>rAX Iz</opr>
- <syn>sext</syn>
</del><ins>+ <opr>rAX sIz</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -5194,38 +5421,37 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>81 /reg=1</opc>
</span><del>- <opr>Ev Iz</opr>
- <syn>sext</syn>
</del><ins>+ <opr>Ev sIz</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>82 /reg=1</opc>
</del><ins>+ <opc>82 /reg=1 /m=!64</opc>
</ins><span class="cx"> <opr>Eb Ib</opr>
</span><del>- <mode>inv64</mode>
</del><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>83 /reg=1</opc>
</span><del>- <opr>Ev Ib</opr>
- <syn>sext</syn>
</del><ins>+ <opr>Ev sIb</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>orpd</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 56</opc>
- <opr>V W</opr>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 56</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>orps</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
</ins><span class="cx"> <opc>0f 56</opc>
</span><del>- <opr>V W</opr>
</del><ins>+ <opr>V H W</opr>
+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -5254,6 +5480,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>outsb</mnemonic>
</span><span class="cx"> <def>
</span><ins>+ <pfx>rep seg</pfx>
</ins><span class="cx"> <opc>6e</opc>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -5261,7 +5488,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>outsw</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>oso</pfx>
</del><ins>+ <pfx>rep oso seg</pfx>
</ins><span class="cx"> <opc>6f /o=16</opc>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -5269,72 +5496,72 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>outsd</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>oso</pfx>
</del><ins>+ <pfx>rep oso seg</pfx>
</ins><span class="cx"> <opc>6f /o=32</opc>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><del>- <mnemonic>outsq</mnemonic>
- <def>
- <pfx>oso</pfx>
- <opc>6f /o=64</opc>
- </def>
- </instruction>
-
- <instruction>
</del><span class="cx"> <mnemonic>packsswb</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 63</opc>
- <opr>V W</opr>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 63</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>0f 63</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><ins>+ <cpuid>mmx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>packssdw</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 6b</opc>
- <opr>V W</opr>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 6b</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>0f 6b</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><ins>+ <cpuid>mmx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>packuswb</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 67</opc>
- <opr>V W</opr>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 67</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>0f 67</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><ins>+ <cpuid>mmx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>paddb</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f fc</opc>
- <opr>V W</opr>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f fc</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>0f fc</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><ins>+ <cpuid>mmx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -5344,11 +5571,13 @@
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>0f fd</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><ins>+ <cpuid>mmx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f fd</opc>
- <opr>V W</opr>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f fd</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -5358,11 +5587,13 @@
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>0f fe</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><ins>+ <cpuid>mmx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f fe</opc>
- <opr>V W</opr>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f fe</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -5376,8 +5607,9 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f ec</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f ec</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -5390,8 +5622,9 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f ed</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f ed</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -5404,8 +5637,9 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f dc</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f dc</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -5418,8 +5652,9 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f dd</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f dd</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -5427,8 +5662,9 @@
</span><span class="cx"> <mnemonic>pand</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f db</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f db</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -5441,8 +5677,9 @@
</span><span class="cx"> <mnemonic>pandn</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f df</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f df</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -5455,8 +5692,9 @@
</span><span class="cx"> <mnemonic>pavgb</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f e0</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f e0</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -5469,8 +5707,9 @@
</span><span class="cx"> <mnemonic>pavgw</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f e3</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f e3</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -5488,8 +5727,9 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 74</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 74</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -5502,8 +5742,9 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 75</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 75</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -5516,8 +5757,9 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 76</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 76</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -5525,8 +5767,9 @@
</span><span class="cx"> <mnemonic>pcmpgtb</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 64</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 64</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -5539,8 +5782,9 @@
</span><span class="cx"> <mnemonic>pcmpgtw</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 65</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 65</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -5553,8 +5797,9 @@
</span><span class="cx"> <mnemonic>pcmpgtd</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 66</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 66</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -5566,24 +5811,27 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>pextrb</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexb</pfx>
- <opc>sse66 0f 3a 14</opc>
</del><ins>+ <pfx>aso rexx rexr rexb</pfx>
+ <opc>/sse=66 0f 3a 14 /vexw=0</opc>
</ins><span class="cx"> <opr>MbRv V Ib</opr>
</span><span class="cx"> <mode>def64</mode>
</span><ins>+ <cpuid>sse4.1 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>pextrd</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexw rexb</pfx>
- <opc>sse66 0f 3a 16 /o=16</opc>
- <opr>Ev V Ib</opr>
</del><ins>+ <pfx>aso rexr rexx rexw rexb</pfx>
+ <opc>/sse=66 0f 3a 16 /o=16 /vexw=0</opc>
+ <opr>Ed V Ib</opr>
+ <cpuid>sse4.1 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexw rexb</pfx>
- <opc>sse66 0f 3a 16 /o=32</opc>
- <opr>Ev V Ib</opr>
</del><ins>+ <pfx>aso rexr rexx rexw rexb</pfx>
+ <opc>/sse=66 0f 3a 16 /o=32 /vexw=0</opc>
+ <opr>Ed V Ib</opr>
+ <cpuid>sse4.1 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -5591,41 +5839,127 @@
</span><span class="cx"> <mnemonic>pextrq</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexw rexb</pfx>
</span><del>- <opc>sse66 0f 3a 16 /o=64</opc>
- <opr>Ev V Ib</opr>
</del><ins>+ <opc>/sse=66 0f 3a 16 /o=64 /vexw=1</opc>
+ <opr>Eq V Ib</opr>
</ins><span class="cx"> <mode>def64</mode>
</span><ins>+ <cpuid>sse4.1 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>pextrw</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexb</pfx>
- <opc>sse66 0f c5</opc>
- <opr>Gd VR Ib</opr>
</del><ins>+ <pfx>aso rexw rexr rexb</pfx>
+ <opc>/sse=66 0f c5</opc>
+ <opr>Gd U Ib</opr>
+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <pfx>aso oso rexw rexr rexx rexb</pfx>
</del><ins>+ <pfx>aso rexw rexr rexx rexb</pfx>
</ins><span class="cx"> <opc>0f c5</opc>
</span><del>- <opr>Gd PR Ib</opr>
</del><ins>+ <opr>Gd N Ib</opr>
</ins><span class="cx"> </def>
</span><ins>+ <def>
+ <pfx>aso rexw rexx rexr rexb</pfx>
+ <opc>/sse=66 0f 3a 15</opc>
+ <opr>MwRd V Ib</opr>
+ <cpuid>sse4.1 avx</cpuid>
+ </def>
</ins><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><ins>+ <mnemonic>pinsrb</mnemonic>
+ <def>
+ <pfx>aso rexw rexr rexx rexb</pfx>
+ <opc>/sse=66 0f 3a 20</opc>
+ <opr>V MbRd Ib</opr>
+ <cpuid>sse4.1</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
</ins><span class="cx"> <mnemonic>pinsrw</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso oso rexw rexr rexx rexb</pfx>
</del><ins>+ <pfx>aso rexw rexr rexx rexb</pfx>
</ins><span class="cx"> <opc>0f c4</opc>
</span><del>- <opr>P Ew Ib</opr>
</del><ins>+ <opr>P MwRy Ib</opr>
+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexw rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f c4</opc>
- <opr>V Ew Ib</opr>
</del><ins>+ <opc>/sse=66 0f c4</opc>
+ <opr>V MwRy Ib</opr>
+ <mode>def64</mode>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><ins>+ <mnemonic>pinsrd</mnemonic>
+ <def>
+ <pfx>aso rexw rexr rexx rexb</pfx>
+ <opc>/sse=66 0f 3a 22 /o=16</opc>
+ <opr>V Ed Ib</opr>
+ <cpuid>sse4.1</cpuid>
+ </def>
+
+ <def>
+ <pfx>aso rexw rexr rexx rexb</pfx>
+ <opc>/sse=66 0f 3a 22 /o=32</opc>
+ <opr>V Ed Ib</opr>
+ <cpuid>sse4.1</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>pinsrq</mnemonic>
+ <def>
+ <pfx>aso oso rexw rexr rexx rexb</pfx>
+ <opc>/sse=66 0f 3a 22 /o=64</opc>
+ <opr>V Eq Ib</opr>
+ <cpuid>sse4.1</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>vpinsrb</mnemonic>
+ <def>
+ <pfx>aso rexw rexr rexx rexb</pfx>
+ <opc>/vex=66_0f3a 20 /vexw=0 /vexl=0</opc>
+ <opr>V H MbRd Ib</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>vpinsrd</mnemonic>
+ <def>
+ <pfx>aso oso rexw rexr rexx rexb</pfx>
+ <opc>/vex=66_0f3a 22 /m=!64 /vexw=0 /vexl=0</opc>
+ <opr>V H Ed Ib</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ <def>
+ <pfx>aso oso rexw rexr rexx rexb</pfx>
+ <opc>/vex=66_0f3a 22 /m=64 /vexw=0 /vexl=0</opc>
+ <opr>V H Ed Ib</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ </instruction>
+
+
+ <instruction>
+ <mnemonic>vpinsrq</mnemonic>
+ <def>
+ <pfx>aso oso rexw rexr rexx rexb</pfx>
+ <opc>/vex=66_0f3a 22 /m=64 /vexw=1 /vexl=0</opc>
+ <opr>V H Eq Ib</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ </instruction>
+
+
+ <instruction>
</ins><span class="cx"> <mnemonic>pmaddwd</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -5634,8 +5968,9 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f f5</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f f5</opc>
+ <opr>V H W</opr>
+ <cpuid>sse4.1 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -5643,8 +5978,9 @@
</span><span class="cx"> <mnemonic>pmaxsw</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f ee</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f ee</opc>
+ <opr>V H W</opr>
+ <cpuid>sse4.1 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -5662,8 +5998,9 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f de</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f de</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -5671,8 +6008,9 @@
</span><span class="cx"> <mnemonic>pminsw</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f ea</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f ea</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -5685,8 +6023,9 @@
</span><span class="cx"> <mnemonic>pminub</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f da</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f da</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -5698,14 +6037,15 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>pmovmskb</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>rexr rexb</pfx>
- <opc>sse66 0f d7</opc>
- <opr>Gd VR</opr>
</del><ins>+ <pfx>oso rexr rexw rexb</pfx>
+ <opc>/sse=66 0f d7 /vexl=0</opc>
+ <opr>Gd U</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <pfx>oso rexr rexb</pfx>
</del><ins>+ <pfx>oso rexr rexw rexb</pfx>
</ins><span class="cx"> <opc>0f d7</opc>
</span><del>- <opr>Gd PR</opr>
</del><ins>+ <opr>Gd N</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -5718,8 +6058,9 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f e4</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f e4</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -5727,8 +6068,9 @@
</span><span class="cx"> <mnemonic>pmulhw</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f e5</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f e5</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -5746,25 +6088,26 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f d5</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f d5</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>pop</mnemonic>
</span><span class="cx"> <def>
</span><del>- <opc>07</opc>
</del><ins>+ <opc>07 /m=!64</opc>
</ins><span class="cx"> <opr>ES</opr>
</span><span class="cx"> <mode>inv64</mode>
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <opc>17</opc>
</del><ins>+ <opc>17 /m=!64</opc>
</ins><span class="cx"> <opr>SS</opr>
</span><span class="cx"> <mode>inv64</mode>
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <opc>1f</opc>
</del><ins>+ <opc>1f /m=!64</opc>
</ins><span class="cx"> <opr>DS</opr>
</span><span class="cx"> <mode>inv64</mode>
</span><span class="cx"> </def>
</span><span class="lines">@@ -5779,56 +6122,56 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexb</pfx>
</span><span class="cx"> <opc>58</opc>
</span><del>- <opr>rAXr8</opr>
- <mode>def64 depM</mode>
</del><ins>+ <opr>R0v</opr>
+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexb</pfx>
</span><span class="cx"> <opc>59</opc>
</span><del>- <opr>rCXr9</opr>
- <mode>def64 depM</mode>
</del><ins>+ <opr>R1v</opr>
+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexb</pfx>
</span><span class="cx"> <opc>5a</opc>
</span><del>- <opr>rDXr10</opr>
- <mode>def64 depM</mode>
</del><ins>+ <opr>R2v</opr>
+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexb</pfx>
</span><span class="cx"> <opc>5b</opc>
</span><del>- <opr>rBXr11</opr>
- <mode>def64 depM</mode>
</del><ins>+ <opr>R3v</opr>
+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexb</pfx>
</span><span class="cx"> <opc>5c</opc>
</span><del>- <opr>rSPr12</opr>
- <mode>def64 depM</mode>
</del><ins>+ <opr>R4v</opr>
+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexb</pfx>
</span><span class="cx"> <opc>5d</opc>
</span><del>- <opr>rBPr13</opr>
- <mode>def64 depM</mode>
</del><ins>+ <opr>R5v</opr>
+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexb</pfx>
</span><span class="cx"> <opc>5e</opc>
</span><del>- <opr>rSIr14</opr>
- <mode>def64 depM</mode>
</del><ins>+ <opr>R6v</opr>
+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexb</pfx>
</span><span class="cx"> <opc>5f</opc>
</span><del>- <opr>rDIr15</opr>
- <mode>def64 depM</mode>
</del><ins>+ <opr>R7v</opr>
+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>8f /reg=0</opc>
</span><span class="cx"> <opr>Ev</opr>
</span><del>- <mode>def64 depM</mode>
</del><ins>+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -5836,7 +6179,7 @@
</span><span class="cx"> <mnemonic>popa</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso</pfx>
</span><del>- <opc>61 /o=16</opc>
</del><ins>+ <opc>61 /o=16 /m=!64</opc>
</ins><span class="cx"> <mode>inv64</mode>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -5845,7 +6188,7 @@
</span><span class="cx"> <mnemonic>popad</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso</pfx>
</span><del>- <opc>61 /o=32</opc>
</del><ins>+ <opc>61 /o=32 /m=!64</opc>
</ins><span class="cx"> <mode>inv64</mode>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -5854,36 +6197,29 @@
</span><span class="cx"> <mnemonic>popfw</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso</pfx>
</span><del>- <opc>9d /m=32 /o=16</opc>
- <mode>def64 depM</mode>
</del><ins>+ <opc>9d /m=!64 /o=16</opc>
</ins><span class="cx"> </def>
</span><del>- <def>
- <pfx>oso</pfx>
- <opc>9d /m=16 /o=16</opc>
- <mode>def64 depM</mode>
- </def>
</del><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>popfd</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso</pfx>
</span><del>- <opc>9d /m=16 /o=32</opc>
- <mode>def64 depM</mode>
</del><ins>+ <opc>9d /m=!64 /o=32</opc>
</ins><span class="cx"> </def>
</span><del>- <def>
- <pfx>oso</pfx>
- <opc>9d /m=32 /o=32</opc>
- <mode>def64 depM</mode>
- </def>
</del><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>popfq</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso</pfx>
</span><ins>+ <opc>9d /m=64 /o=32</opc>
+ <mode>def64</mode>
+ </def>
+ <def>
+ <pfx>oso</pfx>
</ins><span class="cx"> <opc>9d /m=64 /o=64</opc>
</span><del>- <mode>def64 depM</mode>
</del><ins>+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -5891,8 +6227,9 @@
</span><span class="cx"> <mnemonic>por</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f eb</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f eb</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -5985,8 +6322,9 @@
</span><span class="cx"> <mnemonic>psadbw</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f f6</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f f6</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -6004,12 +6342,13 @@
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><del>- <instruction>
</del><ins>+ <instruction>
</ins><span class="cx"> <mnemonic>psllw</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f f1</opc>
</del><ins>+ <opc>/sse=66 0f f1</opc>
</ins><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>sse2</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -6018,12 +6357,13 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>rexb</pfx>
</span><del>- <opc>sse66 0f 71 /reg=6</opc>
- <opr>VR Ib</opr>
</del><ins>+ <opc>/sse=66 0f 71 /reg=6</opc>
+ <opr>U Ib</opr>
+ <cpuid>sse2</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <opc>0f 71 /reg=6</opc>
</span><del>- <opr>PR Ib</opr>
</del><ins>+ <opr>N Ib</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -6031,8 +6371,9 @@
</span><span class="cx"> <mnemonic>pslld</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f f2</opc>
</del><ins>+ <opc>/sse=66 0f f2</opc>
</ins><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>sse2</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -6041,12 +6382,13 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>rexb</pfx>
</span><del>- <opc>sse66 0f 72 /reg=6</opc>
- <opr>VR Ib</opr>
</del><ins>+ <opc>/sse=66 0f 72 /reg=6</opc>
+ <opr>U Ib</opr>
+ <cpuid>sse2</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <opc>0f 72 /reg=6</opc>
</span><del>- <opr>PR Ib</opr>
</del><ins>+ <opr>N Ib</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -6054,8 +6396,9 @@
</span><span class="cx"> <mnemonic>psllq</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f f3</opc>
</del><ins>+ <opc>/sse=66 0f f3</opc>
</ins><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>sse2</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -6064,12 +6407,13 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>rexb</pfx>
</span><del>- <opc>sse66 0f 73 /reg=6</opc>
- <opr>VR Ib</opr>
</del><ins>+ <opc>/sse=66 0f 73 /reg=6</opc>
+ <opr>U Ib</opr>
+ <cpuid>sse2</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <opc>0f 73 /reg=6</opc>
</span><del>- <opr>PR Ib</opr>
</del><ins>+ <opr>N Ib</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -6082,17 +6426,19 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f e1</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f e1</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>rexb</pfx>
</span><del>- <opc>sse66 0f 71 /reg=4</opc>
- <opr>VR Ib</opr>
</del><ins>+ <opc>/sse=66 0f 71 /reg=4</opc>
+ <opr>H U Ib</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <opc>0f 71 /reg=4</opc>
</span><del>- <opr>PR Ib</opr>
</del><ins>+ <opr>N Ib</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -6100,12 +6446,13 @@
</span><span class="cx"> <mnemonic>psrad</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <opc>0f 72 /reg=4</opc>
</span><del>- <opr>PR Ib</opr>
</del><ins>+ <opr>N Ib</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f e2</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f e2</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -6114,8 +6461,9 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>rexb</pfx>
</span><del>- <opc>sse66 0f 72 /reg=4</opc>
- <opr>VR Ib</opr>
</del><ins>+ <opc>/sse=66 0f 72 /reg=4</opc>
+ <opr>H U Ib</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -6123,7 +6471,7 @@
</span><span class="cx"> <mnemonic>psrlw</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <opc>0f 71 /reg=2</opc>
</span><del>- <opr>PR Ib</opr>
</del><ins>+ <opr>N Ib</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -6132,13 +6480,15 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f d1</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f d1</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>rexb</pfx>
</span><del>- <opc>sse66 0f 71 /reg=2</opc>
- <opr>VR Ib</opr>
</del><ins>+ <opc>/sse=66 0f 71 /reg=2</opc>
+ <opr>H U Ib</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -6146,7 +6496,7 @@
</span><span class="cx"> <mnemonic>psrld</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <opc>0f 72 /reg=2</opc>
</span><del>- <opr>PR Ib</opr>
</del><ins>+ <opr>N Ib</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -6155,13 +6505,15 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f d2</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f d2</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>rexb</pfx>
</span><del>- <opc>sse66 0f 72 /reg=2</opc>
- <opr>VR Ib</opr>
</del><ins>+ <opc>/sse=66 0f 72 /reg=2</opc>
+ <opr>H U Ib</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -6169,7 +6521,7 @@
</span><span class="cx"> <mnemonic>psrlq</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <opc>0f 73 /reg=2</opc>
</span><del>- <opr>PR Ib</opr>
</del><ins>+ <opr>N Ib</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -6178,13 +6530,15 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f d3</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f d3</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>rexb</pfx>
</span><del>- <opc>sse66 0f 73 /reg=2</opc>
- <opr>VR Ib</opr>
</del><ins>+ <opc>/sse=66 0f 73 /reg=2</opc>
+ <opr>H U Ib</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -6192,8 +6546,9 @@
</span><span class="cx"> <mnemonic>psubb</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f f8</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f f8</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -6206,8 +6561,9 @@
</span><span class="cx"> <mnemonic>psubw</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f f9</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f f9</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -6225,8 +6581,9 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f fa</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f fa</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -6239,8 +6596,9 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f e8</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f e8</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -6253,8 +6611,9 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f e9</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f e9</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -6267,8 +6626,9 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f d8</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f d8</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -6281,8 +6641,9 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f d9</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f d9</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -6290,8 +6651,9 @@
</span><span class="cx"> <mnemonic>punpckhbw</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 68</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 68</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -6304,8 +6666,9 @@
</span><span class="cx"> <mnemonic>punpckhwd</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 69</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 69</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -6318,8 +6681,9 @@
</span><span class="cx"> <mnemonic>punpckhdq</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 6a</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 6a</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -6332,8 +6696,9 @@
</span><span class="cx"> <mnemonic>punpcklbw</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 60</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 60</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -6346,8 +6711,9 @@
</span><span class="cx"> <mnemonic>punpcklwd</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 61</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 61</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -6360,8 +6726,9 @@
</span><span class="cx"> <mnemonic>punpckldq</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 62</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 62</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -6373,6 +6740,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>pi2fw</mnemonic>
</span><span class="cx"> <def>
</span><ins>+ <pfx>aso rexr rexx rexb</pfx>
</ins><span class="cx"> <opc>0f 0f /3dnow=0c</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><span class="cx"> </def>
</span><span class="lines">@@ -6381,6 +6749,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>pi2fd</mnemonic>
</span><span class="cx"> <def>
</span><ins>+ <pfx>aso rexr rexx rexb</pfx>
</ins><span class="cx"> <opc>0f 0f /3dnow=0d</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><span class="cx"> </def>
</span><span class="lines">@@ -6389,6 +6758,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>pf2iw</mnemonic>
</span><span class="cx"> <def>
</span><ins>+ <pfx>aso rexr rexx rexb</pfx>
</ins><span class="cx"> <opc>0f 0f /3dnow=1c</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><span class="cx"> </def>
</span><span class="lines">@@ -6397,6 +6767,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>pf2id</mnemonic>
</span><span class="cx"> <def>
</span><ins>+ <pfx>aso rexr rexx rexb</pfx>
</ins><span class="cx"> <opc>0f 0f /3dnow=1d</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><span class="cx"> </def>
</span><span class="lines">@@ -6405,6 +6776,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>pfnacc</mnemonic>
</span><span class="cx"> <def>
</span><ins>+ <pfx>aso rexr rexx rexb</pfx>
</ins><span class="cx"> <opc>0f 0f /3dnow=8a</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><span class="cx"> </def>
</span><span class="lines">@@ -6413,6 +6785,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>pfpnacc</mnemonic>
</span><span class="cx"> <def>
</span><ins>+ <pfx>aso rexr rexx rexb</pfx>
</ins><span class="cx"> <opc>0f 0f /3dnow=8e</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><span class="cx"> </def>
</span><span class="lines">@@ -6421,6 +6794,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>pfcmpge</mnemonic>
</span><span class="cx"> <def>
</span><ins>+ <pfx>aso rexr rexx rexb</pfx>
</ins><span class="cx"> <opc>0f 0f /3dnow=90</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><span class="cx"> </def>
</span><span class="lines">@@ -6429,6 +6803,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>pfmin</mnemonic>
</span><span class="cx"> <def>
</span><ins>+ <pfx>aso rexr rexx rexb</pfx>
</ins><span class="cx"> <opc>0f 0f /3dnow=94</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><span class="cx"> </def>
</span><span class="lines">@@ -6437,6 +6812,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>pfrcp</mnemonic>
</span><span class="cx"> <def>
</span><ins>+ <pfx>aso rexr rexx rexb</pfx>
</ins><span class="cx"> <opc>0f 0f /3dnow=96</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><span class="cx"> </def>
</span><span class="lines">@@ -6445,6 +6821,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>pfrsqrt</mnemonic>
</span><span class="cx"> <def>
</span><ins>+ <pfx>aso rexr rexx rexb</pfx>
</ins><span class="cx"> <opc>0f 0f /3dnow=97</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><span class="cx"> </def>
</span><span class="lines">@@ -6453,6 +6830,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>pfsub</mnemonic>
</span><span class="cx"> <def>
</span><ins>+ <pfx>aso rexr rexx rexb</pfx>
</ins><span class="cx"> <opc>0f 0f /3dnow=9a</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><span class="cx"> </def>
</span><span class="lines">@@ -6461,6 +6839,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>pfadd</mnemonic>
</span><span class="cx"> <def>
</span><ins>+ <pfx>aso rexr rexx rexb</pfx>
</ins><span class="cx"> <opc>0f 0f /3dnow=9e</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><span class="cx"> </def>
</span><span class="lines">@@ -6469,6 +6848,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>pfcmpgt</mnemonic>
</span><span class="cx"> <def>
</span><ins>+ <pfx>aso rexr rexx rexb</pfx>
</ins><span class="cx"> <opc>0f 0f /3dnow=a0</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><span class="cx"> </def>
</span><span class="lines">@@ -6477,6 +6857,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>pfmax</mnemonic>
</span><span class="cx"> <def>
</span><ins>+ <pfx>aso rexr rexx rexb</pfx>
</ins><span class="cx"> <opc>0f 0f /3dnow=a4</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><span class="cx"> </def>
</span><span class="lines">@@ -6485,6 +6866,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>pfrcpit1</mnemonic>
</span><span class="cx"> <def>
</span><ins>+ <pfx>aso rexr rexx rexb</pfx>
</ins><span class="cx"> <opc>0f 0f /3dnow=a6</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><span class="cx"> </def>
</span><span class="lines">@@ -6493,6 +6875,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>pfrsqit1</mnemonic>
</span><span class="cx"> <def>
</span><ins>+ <pfx>aso rexr rexx rexb</pfx>
</ins><span class="cx"> <opc>0f 0f /3dnow=a7</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><span class="cx"> </def>
</span><span class="lines">@@ -6501,6 +6884,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>pfsubr</mnemonic>
</span><span class="cx"> <def>
</span><ins>+ <pfx>aso rexr rexx rexb</pfx>
</ins><span class="cx"> <opc>0f 0f /3dnow=aa</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><span class="cx"> </def>
</span><span class="lines">@@ -6509,6 +6893,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>pfacc</mnemonic>
</span><span class="cx"> <def>
</span><ins>+ <pfx>aso rexr rexx rexb</pfx>
</ins><span class="cx"> <opc>0f 0f /3dnow=ae</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><span class="cx"> </def>
</span><span class="lines">@@ -6517,6 +6902,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>pfcmpeq</mnemonic>
</span><span class="cx"> <def>
</span><ins>+ <pfx>aso rexr rexx rexb</pfx>
</ins><span class="cx"> <opc>0f 0f /3dnow=b0</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><span class="cx"> </def>
</span><span class="lines">@@ -6525,6 +6911,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>pfmul</mnemonic>
</span><span class="cx"> <def>
</span><ins>+ <pfx>aso rexr rexx rexb</pfx>
</ins><span class="cx"> <opc>0f 0f /3dnow=b4</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><span class="cx"> </def>
</span><span class="lines">@@ -6533,6 +6920,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>pfrcpit2</mnemonic>
</span><span class="cx"> <def>
</span><ins>+ <pfx>aso rexr rexx rexb</pfx>
</ins><span class="cx"> <opc>0f 0f /3dnow=b6</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><span class="cx"> </def>
</span><span class="lines">@@ -6541,6 +6929,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>pmulhrw</mnemonic>
</span><span class="cx"> <def>
</span><ins>+ <pfx>aso rexr rexx rexb</pfx>
</ins><span class="cx"> <opc>0f 0f /3dnow=b7</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><span class="cx"> </def>
</span><span class="lines">@@ -6549,6 +6938,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>pswapd</mnemonic>
</span><span class="cx"> <def>
</span><ins>+ <pfx>aso rexr rexx rexb</pfx>
</ins><span class="cx"> <opc>0f 0f /3dnow=bb</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><span class="cx"> </def>
</span><span class="lines">@@ -6557,6 +6947,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>pavgusb</mnemonic>
</span><span class="cx"> <def>
</span><ins>+ <pfx>aso rexr rexx rexb</pfx>
</ins><span class="cx"> <opc>0f 0f /3dnow=bf</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><span class="cx"> </def>
</span><span class="lines">@@ -6565,22 +6956,22 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>push</mnemonic>
</span><span class="cx"> <def>
</span><del>- <opc>06</opc>
</del><ins>+ <opc>06 /m=!64</opc>
</ins><span class="cx"> <opr>ES</opr>
</span><span class="cx"> <mode>inv64</mode>
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <opc>0e</opc>
</del><ins>+ <opc>0e /m=!64</opc>
</ins><span class="cx"> <opr>CS</opr>
</span><span class="cx"> <mode>inv64</mode>
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <opc>16</opc>
</del><ins>+ <opc>16 /m=!64</opc>
</ins><span class="cx"> <opr>SS</opr>
</span><span class="cx"> <mode>inv64</mode>
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <opc>1e</opc>
</del><ins>+ <opc>1e /m=!64</opc>
</ins><span class="cx"> <opr>DS</opr>
</span><span class="cx"> <mode>inv64</mode>
</span><span class="cx"> </def>
</span><span class="lines">@@ -6595,56 +6986,56 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexb</pfx>
</span><span class="cx"> <opc>50</opc>
</span><del>- <opr>rAXr8</opr>
- <mode>def64 depM</mode>
</del><ins>+ <opr>R0v</opr>
+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexb</pfx>
</span><span class="cx"> <opc>51</opc>
</span><del>- <opr>rCXr9</opr>
- <mode>def64 depM</mode>
</del><ins>+ <opr>R1v</opr>
+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexb</pfx>
</span><span class="cx"> <opc>52</opc>
</span><del>- <opr>rDXr10</opr>
- <mode>def64 depM</mode>
</del><ins>+ <opr>R2v</opr>
+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexb</pfx>
</span><span class="cx"> <opc>53</opc>
</span><del>- <opr>rBXr11</opr>
- <mode>def64 depM</mode>
</del><ins>+ <opr>R3v</opr>
+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexb</pfx>
</span><span class="cx"> <opc>54</opc>
</span><del>- <opr>rSPr12</opr>
- <mode>def64 depM</mode>
</del><ins>+ <opr>R4v</opr>
+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexb</pfx>
</span><span class="cx"> <opc>55</opc>
</span><del>- <opr>rBPr13</opr>
- <mode>def64 depM</mode>
</del><ins>+ <opr>R5v</opr>
+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexb</pfx>
</span><span class="cx"> <opc>56</opc>
</span><del>- <opr>rSIr14</opr>
- <mode>def64 depM</mode>
</del><ins>+ <opr>R6v</opr>
+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexb</pfx>
</span><span class="cx"> <opc>57</opc>
</span><del>- <opr>rDIr15</opr>
- <mode>def64 depM</mode>
</del><ins>+ <opr>R7v</opr>
+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso</pfx>
</span><span class="cx"> <opc>68</opc>
</span><del>- <opr>Iz</opr>
- <syn>cast</syn>
</del><ins>+ <opr>sIz</opr>
+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="lines">@@ -6653,9 +7044,10 @@
</span><span class="cx"> <mode>def64</mode>
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><ins>+ <pfx>oso</pfx>
</ins><span class="cx"> <opc>6a</opc>
</span><del>- <opr>Ib</opr>
- <syn>sext</syn>
</del><ins>+ <opr>sIb</opr>
+ <mode>def64</mode>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -6663,7 +7055,7 @@
</span><span class="cx"> <mnemonic>pusha</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso</pfx>
</span><del>- <opc>60 /o=16</opc>
</del><ins>+ <opc>60 /o=16 /m=!64</opc>
</ins><span class="cx"> <mode>inv64</mode>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -6672,7 +7064,7 @@
</span><span class="cx"> <mnemonic>pushad</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso</pfx>
</span><del>- <opc>60 /o=32</opc>
</del><ins>+ <opc>60 /o=32 /m=!64</opc>
</ins><span class="cx"> <mode>inv64</mode>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -6681,15 +7073,9 @@
</span><span class="cx"> <mnemonic>pushfw</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso</pfx>
</span><del>- <opc>9c /m=32 /o=16</opc>
- <mode>def64</mode>
</del><ins>+ <opc>9c /m=!64 /o=16</opc>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <pfx>oso</pfx>
- <opc>9c /m=16 /o=16</opc>
- <mode>def64</mode>
- </def>
- <def>
</del><span class="cx"> <pfx>oso rexw</pfx>
</span><span class="cx"> <opc>9c /m=64 /o=16</opc>
</span><span class="cx"> <mode>def64</mode>
</span><span class="lines">@@ -6700,14 +7086,8 @@
</span><span class="cx"> <mnemonic>pushfd</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso</pfx>
</span><del>- <opc>9c /m=16 /o=32</opc>
- <mode>def64</mode>
</del><ins>+ <opc>9c /m=!64 /o=32</opc>
</ins><span class="cx"> </def>
</span><del>- <def>
- <pfx>oso</pfx>
- <opc>9c /m=32 /o=32</opc>
- <mode>def64</mode>
- </def>
</del><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="lines">@@ -6728,8 +7108,9 @@
</span><span class="cx"> <mnemonic>pxor</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f ef</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f ef</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -6759,13 +7140,11 @@
</span><span class="cx"> <pfx>aso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>d2 /reg=2</opc>
</span><span class="cx"> <opr>Eb CL</opr>
</span><del>- <syn>cast</syn>
</del><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>d3 /reg=2</opc>
</span><span class="cx"> <opr>Ev CL</opr>
</span><del>- <syn>cast</syn>
</del><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="lines">@@ -6800,13 +7179,11 @@
</span><span class="cx"> <pfx>aso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>d2 /reg=3</opc>
</span><span class="cx"> <opr>Eb CL</opr>
</span><del>- <syn>cast</syn>
</del><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>d3 /reg=3</opc>
</span><span class="cx"> <opr>Ev CL</opr>
</span><del>- <syn>cast</syn>
</del><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -6831,13 +7208,11 @@
</span><span class="cx"> <pfx>aso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>d2 /reg=0</opc>
</span><span class="cx"> <opr>Eb CL</opr>
</span><del>- <syn>cast</syn>
</del><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>d3 /reg=0</opc>
</span><span class="cx"> <opr>Ev CL</opr>
</span><del>- <syn>cast</syn>
</del><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="lines">@@ -6872,22 +7247,21 @@
</span><span class="cx"> <pfx>aso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>d2 /reg=1</opc>
</span><span class="cx"> <opr>Eb CL</opr>
</span><del>- <syn>cast</syn>
</del><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>d3 /reg=1</opc>
</span><span class="cx"> <opr>Ev CL</opr>
</span><del>- <syn>cast</syn>
</del><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>rcpps</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
</ins><span class="cx"> <opc>0f 53</opc>
</span><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -6895,8 +7269,9 @@
</span><span class="cx"> <mnemonic>rcpss</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>ssef3 0f 53</opc>
</del><ins>+ <opc>/sse=f3 0f 53</opc>
</ins><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -6975,9 +7350,10 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>rsqrtps</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
</ins><span class="cx"> <opc>0f 52</opc>
</span><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -6985,8 +7361,9 @@
</span><span class="cx"> <mnemonic>rsqrtss</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>ssef3 0f 52</opc>
</del><ins>+ <opc>/sse=f3 0f 52</opc>
</ins><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -7004,7 +7381,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>salc</mnemonic>
</span><span class="cx"> <def>
</span><del>- <opc>d6</opc>
</del><ins>+ <opc>d6 /m=!64</opc>
</ins><span class="cx"> <mode>inv64</mode>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -7035,13 +7412,11 @@
</span><span class="cx"> <pfx>aso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>d2 /reg=7</opc>
</span><span class="cx"> <opr>Eb CL</opr>
</span><del>- <syn>cast</syn>
</del><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>d3 /reg=7</opc>
</span><span class="cx"> <opr>Ev CL</opr>
</span><del>- <syn>cast</syn>
</del><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -7066,13 +7441,11 @@
</span><span class="cx"> <pfx>aso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>d2 /reg=6</opc>
</span><span class="cx"> <opr>Eb CL</opr>
</span><del>- <syn>cast</syn>
</del><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>d3 /reg=6</opc>
</span><span class="cx"> <opr>Ev CL</opr>
</span><del>- <syn>cast</syn>
</del><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="lines">@@ -7083,7 +7456,6 @@
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>d2 /reg=4</opc>
</span><span class="cx"> <opr>Eb CL</opr>
</span><del>- <syn>cast</syn>
</del><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="lines">@@ -7123,7 +7495,6 @@
</span><span class="cx"> <pfx>aso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>d2 /reg=5</opc>
</span><span class="cx"> <opr>Eb CL</opr>
</span><del>- <syn>cast</syn>
</del><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="lines">@@ -7144,7 +7515,6 @@
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>d3 /reg=5</opc>
</span><span class="cx"> <opr>Ev CL</opr>
</span><del>- <syn>cast</syn>
</del><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -7177,8 +7547,7 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexw</pfx>
</span><span class="cx"> <opc>1d</opc>
</span><del>- <opr>rAX Iz</opr>
- <syn>sext</syn>
</del><ins>+ <opr>rAX sIz</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -7188,26 +7557,25 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>81 /reg=3</opc>
</span><del>- <opr>Ev Iz</opr>
- <syn>sext</syn>
</del><ins>+ <opr>Ev sIz</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>82 /reg=3</opc>
</del><ins>+ <opc>82 /reg=3 /m=!64</opc>
</ins><span class="cx"> <opr>Eb Ib</opr>
</span><span class="cx"> <mode>inv64</mode>
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>83 /reg=3</opc>
</span><del>- <opr>Ev Ib</opr>
- <syn>sext</syn>
</del><ins>+ <opr>Ev sIb</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>scasb</mnemonic>
</span><span class="cx"> <def>
</span><ins>+ <pfx>repz</pfx>
</ins><span class="cx"> <opc>ae</opc>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -7215,7 +7583,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>scasw</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>oso rexw</pfx>
</del><ins>+ <pfx>repz oso rexw</pfx>
</ins><span class="cx"> <opc>af /o=16</opc>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -7223,7 +7591,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>scasd</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>oso rexw</pfx>
</del><ins>+ <pfx>repz oso rexw</pfx>
</ins><span class="cx"> <opc>af /o=32</opc>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -7231,7 +7599,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>scasq</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>oso rexw</pfx>
</del><ins>+ <pfx>repz oso rexw</pfx>
</ins><span class="cx"> <opc>af /o=64</opc>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -7264,7 +7632,7 @@
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><del>- <mnemonic>setnb</mnemonic>
</del><ins>+ <mnemonic>setae</mnemonic>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>0f 93</opc>
</span><span class="lines">@@ -7448,9 +7816,10 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>shufpd</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f c6</opc>
- <opr>V W Ib</opr>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f c6</opc>
+ <opr>V H W Ib</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -7459,7 +7828,8 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>0f c6</opc>
</span><del>- <opr>V W Ib</opr>
</del><ins>+ <opr>V H W Ib</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -7475,7 +7845,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>sldt</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso oso rexr rexx rexb</pfx>
</del><ins>+ <pfx>aso oso rexr rexw rexx rexb</pfx>
</ins><span class="cx"> <opc>0f 00 /reg=0</opc>
</span><span class="cx"> <opr>MwRv</opr>
</span><span class="cx"> </def>
</span><span class="lines">@@ -7484,18 +7854,24 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>smsw</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
</del><ins>+ <pfx>aso oso rexr rexw rexx rexb</pfx>
</ins><span class="cx"> <opc>0f 01 /reg=4 /mod=!11</opc>
</span><del>- <opr>M</opr>
</del><ins>+ <opr>MwRv</opr>
</ins><span class="cx"> </def>
</span><ins>+ <def>
+ <pfx>aso oso rexr rexw rexx rexb</pfx>
+ <opc>0f 01 /reg=4 /mod=11</opc>
+ <opr>MwRv</opr>
+ </def>
</ins><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>sqrtps</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
</ins><span class="cx"> <opc>0f 51</opc>
</span><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -7503,8 +7879,9 @@
</span><span class="cx"> <mnemonic>sqrtpd</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 51</opc>
</del><ins>+ <opc>/sse=66 0f 51</opc>
</ins><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -7512,8 +7889,9 @@
</span><span class="cx"> <mnemonic>sqrtsd</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>ssef2 0f 51</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=f2 0f 51</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -7521,8 +7899,9 @@
</span><span class="cx"> <mnemonic>sqrtss</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>ssef3 0f 51</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=f3 0f 51</opc>
+ <opr>V H W</opr>
+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -7567,15 +7946,16 @@
</span><span class="cx"> <mnemonic>stmxcsr</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexw rexr rexx rexb</pfx>
</span><del>- <opc>0f ae /mod=11 /reg=3</opc>
</del><ins>+ <opc>0f ae /mod=!11 /reg=3</opc>
</ins><span class="cx"> <opr>Md</opr>
</span><ins>+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>stosb</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>seg</pfx>
</del><ins>+ <pfx>rep seg</pfx>
</ins><span class="cx"> <opc>aa</opc>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -7583,7 +7963,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>stosw</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>seg oso rexw</pfx>
</del><ins>+ <pfx>rep seg oso rexw</pfx>
</ins><span class="cx"> <opc>ab /o=16</opc>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -7591,7 +7971,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>stosd</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>seg oso rexw</pfx>
</del><ins>+ <pfx>rep seg oso rexw</pfx>
</ins><span class="cx"> <opc>ab /o=32</opc>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -7599,7 +7979,7 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>stosq</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>seg oso rexw</pfx>
</del><ins>+ <pfx>rep seg oso rexw</pfx>
</ins><span class="cx"> <opc>ab /o=64</opc>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -7607,9 +7987,9 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>str</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso oso rexr rexx rexb</pfx>
</del><ins>+ <pfx>aso oso rexr rexw rexx rexb</pfx>
</ins><span class="cx"> <opc>0f 00 /reg=1</opc>
</span><del>- <opr>Ev</opr>
</del><ins>+ <opr>MwRv</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -7642,8 +8022,7 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexw</pfx>
</span><span class="cx"> <opc>2d</opc>
</span><del>- <opr>rAX Iz</opr>
- <syn>sext</syn>
</del><ins>+ <opr>rAX sIz</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -7653,38 +8032,38 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>81 /reg=5</opc>
</span><del>- <opr>Ev Iz</opr>
- <syn>sext</syn>
</del><ins>+ <opr>Ev sIz</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>82 /reg=5</opc>
</del><ins>+ <opc>82 /reg=5 /m=!64</opc>
</ins><span class="cx"> <opr>Eb Ib</opr>
</span><span class="cx"> <mode>inv64</mode>
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>83 /reg=5</opc>
</span><del>- <opr>Ev Ib</opr>
- <syn>sext</syn>
</del><ins>+ <opr>Ev sIb</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>subpd</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 5c</opc>
- <opr>V W</opr>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 5c</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>subps</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
</ins><span class="cx"> <opc>0f 5c</opc>
</span><del>- <opr>V W</opr>
</del><ins>+ <opr>V H W</opr>
+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -7692,8 +8071,9 @@
</span><span class="cx"> <mnemonic>subsd</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>ssef2 0f 5c</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=f2 0f 5c</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -7701,8 +8081,9 @@
</span><span class="cx"> <mnemonic>subss</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>ssef3 0f 5c</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=f3 0f 5c</opc>
+ <opr>V H W</opr>
+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -7723,16 +8104,23 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>sysenter</mnemonic>
</span><span class="cx"> <def>
</span><del>- <opc>0f 34</opc>
- <mode>inv64</mode>
</del><ins>+ <opc>0f 34 /m=!64</opc>
</ins><span class="cx"> </def>
</span><ins>+ <def>
+ <opc>0f 34 /m=64</opc>
+ <vendor>intel</vendor>
+ </def>
</ins><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>sysexit</mnemonic>
</span><span class="cx"> <def>
</span><del>- <opc>0f 35</opc>
</del><ins>+ <opc>0f 35 /m=!64</opc>
</ins><span class="cx"> </def>
</span><ins>+ <def>
+ <opc>0f 35 /m=64</opc>
+ <vendor>intel</vendor>
+ </def>
</ins><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="lines">@@ -7766,8 +8154,7 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexw</pfx>
</span><span class="cx"> <opc>a9</opc>
</span><del>- <opr>rAX Iz</opr>
- <syn>sext</syn>
</del><ins>+ <opr>rAX sIz</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexw rexr rexx rexb</pfx>
</span><span class="lines">@@ -7777,14 +8164,12 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>f7 /reg=0</opc>
</span><del>- <opr>Ev Iz</opr>
- <syn>sext</syn>
</del><ins>+ <opr>Ev sIz</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>f7 /reg=1</opc>
</span><span class="cx"> <opr>Ev Iz</opr>
</span><del>- <syn>sext</syn>
</del><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -7792,8 +8177,9 @@
</span><span class="cx"> <mnemonic>ucomisd</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 2e</opc>
</del><ins>+ <opc>/sse=66 0f 2e</opc>
</ins><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -7803,6 +8189,7 @@
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>0f 2e</opc>
</span><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -7816,9 +8203,10 @@
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>unpckhpd</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 15</opc>
- <opr>V W</opr>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 15</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -7827,7 +8215,8 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>0f 15</opc>
</span><del>- <opr>V W</opr>
</del><ins>+ <opr>V H W</opr>
+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -7836,16 +8225,18 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>0f 14</opc>
</span><del>- <opr>V W</opr>
</del><ins>+ <opr>V H W</opr>
+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>unpcklpd</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 14</opc>
- <opr>V W</opr>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 14</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -7876,11 +8267,21 @@
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><ins>+ <mnemonic>rdrand</mnemonic>
+ <def>
+ <pfx>oso rexr rexw rexx rexb</pfx>
+ <opc>0f c7 /mod=11 /reg=6</opc>
+ <opr>R</opr>
+ </def>
+ <cpuid>rdrand</cpuid>
+ </instruction>
+
+ <instruction>
</ins><span class="cx"> <mnemonic>vmclear</mnemonic>
</span><span class="cx"> <vendor>intel</vendor>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f c7 /reg=6</opc>
</del><ins>+ <opc>/sse=66 0f c7 /mod=!11 /reg=6</opc>
</ins><span class="cx"> <opr>Mq</opr>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -7890,7 +8291,7 @@
</span><span class="cx"> <vendor>intel</vendor>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>ssef3 0f c7 /reg=6</opc>
</del><ins>+ <opc>/sse=f3 0f c7 /mod=!11 /reg=6</opc>
</ins><span class="cx"> <opr>Mq</opr>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -7900,7 +8301,7 @@
</span><span class="cx"> <vendor>intel</vendor>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>0f c7 /reg=6</opc>
</del><ins>+ <opc>0f c7 /mod=!11 /reg=6</opc>
</ins><span class="cx"> <opr>Mq</opr>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -7910,7 +8311,7 @@
</span><span class="cx"> <vendor>intel</vendor>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>0f c7 /reg=7</opc>
</del><ins>+ <opc>0f c7 /mod=!11 /reg=7</opc>
</ins><span class="cx"> <opr>Mq</opr>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -7944,22 +8345,10 @@
</span><span class="cx"> <vendor>intel</vendor>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>0f 78 /m=16</opc>
- <opr>Ed Gd</opr>
</del><ins>+ <opc>0f 78</opc>
+ <opr>Ey Gy</opr>
</ins><span class="cx"> <mode>def64</mode>
</span><span class="cx"> </def>
</span><del>- <def>
- <pfx>aso rexr rexx rexb</pfx>
- <opc>0f 78 /m=32</opc>
- <opr>Ed Gd</opr>
- <mode>def64</mode>
- </def>
- <def>
- <pfx>aso rexr rexx rexb</pfx>
- <opc>0f 78 /m=64</opc>
- <opr>Eq Gq</opr>
- <mode>def64</mode>
- </def>
</del><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="lines">@@ -7967,22 +8356,10 @@
</span><span class="cx"> <vendor>intel</vendor>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>0f 79 /m=16</opc>
- <opr>Gd Ed</opr>
</del><ins>+ <opc>0f 79</opc>
+ <opr>Gy Ey</opr>
</ins><span class="cx"> <mode>def64</mode>
</span><span class="cx"> </def>
</span><del>- <def>
- <pfx>aso rexr rexx rexb</pfx>
- <opc>0f 79 /m=32</opc>
- <opr>Gd Ed</opr>
- <mode>def64</mode>
- </def>
- <def>
- <pfx>aso rexr rexx rexb</pfx>
- <opc>0f 79 /m=64</opc>
- <opr>Gq Eq</opr>
- <mode>def64</mode>
- </def>
</del><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="lines">@@ -8067,49 +8444,56 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexw rexb</pfx>
</span><span class="cx"> <opc>90</opc>
</span><del>- <opr>rAXr8 rAX</opr>
</del><ins>+ <opr>R0v rAX</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexw rexb</pfx>
</span><span class="cx"> <opc>91</opc>
</span><del>- <opr>rCXr9 rAX</opr>
</del><ins>+ <opr>R1v rAX</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexw rexb</pfx>
</span><span class="cx"> <opc>92</opc>
</span><del>- <opr>rDXr10 rAX</opr>
</del><ins>+ <opr>R2v rAX</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexw rexb</pfx>
</span><span class="cx"> <opc>93</opc>
</span><del>- <opr>rBXr11 rAX</opr>
</del><ins>+ <opr>R3v rAX</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexw rexb</pfx>
</span><span class="cx"> <opc>94</opc>
</span><del>- <opr>rSPr12 rAX</opr>
</del><ins>+ <opr>R4v rAX</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexw rexb</pfx>
</span><span class="cx"> <opc>95</opc>
</span><del>- <opr>rBPr13 rAX</opr>
</del><ins>+ <opr>R5v rAX</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexw rexb</pfx>
</span><span class="cx"> <opc>96</opc>
</span><del>- <opr>rSIr14 rAX</opr>
</del><ins>+ <opr>R6v rAX</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexw rexb</pfx>
</span><span class="cx"> <opc>97</opc>
</span><del>- <opr>rDIr15 rAX</opr>
</del><ins>+ <opr>R7v rAX</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><ins>+ <mnemonic>xgetbv</mnemonic>
+ <def>
+ <opc>0f 01 /mod=11 /reg=2 /rm=0</opc>
+ </def>
+ </instruction>
+
+ <instruction>
</ins><span class="cx"> <mnemonic>xlatb</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>rexw</pfx>
</del><ins>+ <pfx>rexw seg</pfx>
</ins><span class="cx"> <opc>d7</opc>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -8143,8 +8527,7 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>oso rexw</pfx>
</span><span class="cx"> <opc>35</opc>
</span><del>- <opr>rAX Iz</opr>
- <syn>sext</syn>
</del><ins>+ <opr>rAX sIz</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -8154,29 +8537,28 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>81 /reg=6</opc>
</span><del>- <opr>Ev Iz</opr>
- <syn>sext</syn>
</del><ins>+ <opr>Ev sIz</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>82 /reg=6</opc>
</del><ins>+ <opc>82 /reg=6 /m=!64</opc>
</ins><span class="cx"> <opr>Eb Ib</opr>
</span><span class="cx"> <mode>inv64</mode>
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso oso rexw rexr rexx rexb</pfx>
</span><span class="cx"> <opc>83 /reg=6</opc>
</span><del>- <opr>Ev Ib</opr>
- <syn>sext</syn>
</del><ins>+ <opr>Ev sIb</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>xorpd</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 57</opc>
- <opr>V W</opr>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 57</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8185,7 +8567,8 @@
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>0f 57</opc>
</span><del>- <opr>V W</opr>
</del><ins>+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8225,6 +8608,31 @@
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><ins>+ <mnemonic>xrstor</mnemonic>
+ <def>
+ <pfx>aso rexw rexr rexx rexb</pfx>
+ <opc>0f ae /reg=5 /mod=!11</opc>
+ <opr>M</opr>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>xsave</mnemonic>
+ <def>
+ <pfx>aso rexw rexr rexx rexb</pfx>
+ <opc>0f ae /reg=4 /mod=!11</opc>
+ <opr>M</opr>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>xsetbv</mnemonic>
+ <def>
+ <opc>0f 01 /mod=11 /reg=2 /rm=1</opc>
+ </def>
+ </instruction>
+
+ <instruction>
</ins><span class="cx"> <mnemonic>xsha1</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <opc>0f a6 /mod=11 /rm=0 /reg=1</opc>
</span><span class="lines">@@ -8246,56 +8654,86 @@
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><del>- <mnemonic>db</mnemonic>
</del><ins>+ <mnemonic>pclmulqdq</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb</pfx>
+ <opc>/sse=66 0f 3a 44</opc>
+ <opr>V H W Ib</opr>
+ <cpuid>aesni avx</cpuid>
+ </def>
</ins><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <!--
</span><ins>+ SMX
+ -->
+
+ <instruction>
+ <mnemonic>getsec</mnemonic>
+ <cpuid>smx</cpuid>
+ <def>
+ <opc>0f 37</opc>
+ </def>
+ </instruction>
+
+ <!--
</ins><span class="cx"> SSE 2
</span><span class="cx"> -->
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>movdqa</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 7f</opc>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 7f</opc>
</ins><span class="cx"> <opr>W V</opr>
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 6f</opc>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 6f</opc>
</ins><span class="cx"> <opr>V W</opr>
</span><span class="cx"> </def>
</span><ins>+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><ins>+ <mnemonic>maskmovdqu</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb</pfx>
+ <opc>/sse=66 0f f7 /mod=11</opc>
+ <opr>V U</opr>
+ <cpuid>sse2 avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
</ins><span class="cx"> <mnemonic>movdq2q</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexb</pfx>
</span><del>- <opc>ssef2 0f d6</opc>
- <opr>P VR</opr>
</del><ins>+ <opc>/sse=f2 0f d6</opc>
+ <opr>P U</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>movdqu</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>ssef3 0f 6f</opc>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=f3 0f 6f</opc>
</ins><span class="cx"> <opr>V W</opr>
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>ssef3 0f 7f</opc>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=f3 0f 7f</opc>
</ins><span class="cx"> <opr>W V</opr>
</span><span class="cx"> </def>
</span><ins>+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>movq2dq</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso</pfx>
- <opc>ssef3 0f d6</opc>
- <opr>V PR</opr>
</del><ins>+ <pfx>aso rexr</pfx>
+ <opc>/sse=f3 0f d6</opc>
+ <opr>V N</opr>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8308,8 +8746,9 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f d4</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f d4</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8317,8 +8756,9 @@
</span><span class="cx"> <mnemonic>psubq</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f fb</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f fb</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="lines">@@ -8336,7 +8776,7 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f f4</opc>
</del><ins>+ <opc>/sse=66 0f f4</opc>
</ins><span class="cx"> <opr>V W</opr>
</span><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="lines">@@ -8345,8 +8785,9 @@
</span><span class="cx"> <mnemonic>pshufhw</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>ssef3 0f 70</opc>
</del><ins>+ <opc>/sse=f3 0f 70</opc>
</ins><span class="cx"> <opr>V W Ib</opr>
</span><ins>+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8354,8 +8795,9 @@
</span><span class="cx"> <mnemonic>pshuflw</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>ssef2 0f 70</opc>
</del><ins>+ <opc>/sse=f2 0f 70</opc>
</ins><span class="cx"> <opr>V W Ib</opr>
</span><ins>+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8363,8 +8805,9 @@
</span><span class="cx"> <mnemonic>pshufd</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 70</opc>
</del><ins>+ <opc>/sse=66 0f 70</opc>
</ins><span class="cx"> <opr>V W Ib</opr>
</span><ins>+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8372,8 +8815,9 @@
</span><span class="cx"> <mnemonic>pslldq</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>rexb</pfx>
</span><del>- <opc>sse66 0f 73 /reg=7</opc>
- <opr>VR Ib</opr>
</del><ins>+ <opc>/sse=66 0f 73 /reg=7</opc>
+ <opr>H U Ib</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8381,8 +8825,9 @@
</span><span class="cx"> <mnemonic>psrldq</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>rexb</pfx>
</span><del>- <opc>sse66 0f 73 /reg=3</opc>
- <opr>VR Ib</opr>
</del><ins>+ <opc>/sse=66 0f 73 /reg=3</opc>
+ <opr>H U Ib</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8390,8 +8835,9 @@
</span><span class="cx"> <mnemonic>punpckhqdq</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 6d</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 6d</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8399,66 +8845,69 @@
</span><span class="cx"> <mnemonic>punpcklqdq</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 6c</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 6c</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><del>- <!--
- SSE 3
- -->
-
</del><span class="cx"> <instruction>
</span><del>- <mnemonic>addsubpd</mnemonic>
</del><ins>+ <mnemonic>haddpd</mnemonic>
</ins><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f d0</opc>
- <opr>V W</opr>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 7c</opc>
+ <opr>V H W</opr>
+ <cpuid>sse3 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><del>- <mnemonic>addsubps</mnemonic>
</del><ins>+ <mnemonic>haddps</mnemonic>
</ins><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>ssef2 0f d0</opc>
- <opr>V W</opr>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=f2 0f 7c</opc>
+ <opr>V H W</opr>
+ <cpuid>sse3 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><del>- <mnemonic>haddpd</mnemonic>
</del><ins>+ <mnemonic>hsubpd</mnemonic>
</ins><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 7c</opc>
- <opr>V W</opr>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 7d</opc>
+ <opr>V H W</opr>
+ <cpuid>sse3 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><del>- <mnemonic>haddps</mnemonic>
</del><ins>+ <mnemonic>hsubps</mnemonic>
</ins><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>ssef2 0f 7c</opc>
- <opr>V W</opr>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=f2 0f 7d</opc>
+ <opr>V H W</opr>
+ <cpuid>sse3 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><del>- <mnemonic>hsubpd</mnemonic>
</del><ins>+ <mnemonic>insertps</mnemonic>
</ins><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 7d</opc>
- <opr>V W</opr>
</del><ins>+ <pfx>aso rexr rexw rexx rexb</pfx>
+ <opc>/sse=66 0f 3a 21</opc>
+ <opr>V H Md Ib</opr>
+ <cpuid>sse4.1 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><del>- <mnemonic>hsubps</mnemonic>
</del><ins>+ <mnemonic>lddqu</mnemonic>
</ins><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>ssef2 0f 7d</opc>
- <opr>V W</opr>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=f2 0f f0</opc>
+ <opr>V M</opr>
+ <cpuid>sse3 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8466,41 +8915,46 @@
</span><span class="cx"> <mnemonic>movddup</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>ssef2 0f 12 /mod=11</opc>
</del><ins>+ <opc>/sse=f2 0f 12 /mod=11</opc>
</ins><span class="cx"> <opr>V W</opr>
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>ssef2 0f 12 /mod=!11</opc>
</del><ins>+ <opc>/sse=f2 0f 12 /mod=!11</opc>
</ins><span class="cx"> <opr>V W</opr>
</span><span class="cx"> </def>
</span><ins>+ <cpuid>sse3 avx</cpuid>
</ins><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>movshdup</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>ssef3 0f 16 /mod=11</opc>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=f3 0f 16 /mod=11</opc>
</ins><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>sse3 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>ssef3 0f 16 /mod=!11</opc>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=f3 0f 16 /mod=!11</opc>
</ins><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>sse3 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>movsldup</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>ssef3 0f 12 /mod=11</opc>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=f3 0f 12 /mod=11</opc>
</ins><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>sse3 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>ssef3 0f 12 /mod=!11</opc>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=f3 0f 12 /mod=!11</opc>
</ins><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>sse3 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8514,11 +8968,13 @@
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>0f 38 1c</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><ins>+ <cpuid>ssse3</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 38 1c</opc>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 38 1c</opc>
</ins><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>ssse3 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8528,11 +8984,13 @@
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>0f 38 1d</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><ins>+ <cpuid>ssse3</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 38 1d</opc>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 38 1d</opc>
</ins><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>ssse3 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8542,16 +9000,18 @@
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>0f 38 1e</opc>
</span><span class="cx"> <opr>P Q</opr>
</span><ins>+ <cpuid>ssse3</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 38 1e</opc>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 38 1e</opc>
</ins><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>ssse3 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><del>- <mnemonic>psignb</mnemonic>
</del><ins>+ <mnemonic>pshufb</mnemonic>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><span class="cx"> <opc>0f 38 00</opc>
</span><span class="lines">@@ -8559,8 +9019,9 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 38 00</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 38 00</opc>
+ <opr>V H W</opr>
+ <cpuid>ssse3 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8573,8 +9034,9 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 38 01</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 38 01</opc>
+ <opr>V H W</opr>
+ <cpuid>ssse3 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8587,8 +9049,9 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 38 02</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 38 02</opc>
+ <opr>V H W</opr>
+ <cpuid>ssse3 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8601,8 +9064,9 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 38 03</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 38 03</opc>
+ <opr>V H W</opr>
+ <cpuid>ssse3 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8615,8 +9079,9 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 38 04</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 38 04</opc>
+ <opr>V H W</opr>
+ <cpuid>ssse3 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8629,8 +9094,9 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 38 05</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 38 05</opc>
+ <opr>V H W</opr>
+ <cpuid>ssse3 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8643,8 +9109,9 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 38 06</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 38 06</opc>
+ <opr>V H W</opr>
+ <cpuid>ssse3 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8657,8 +9124,9 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 38 07</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 38 07</opc>
+ <opr>V H W</opr>
+ <cpuid>ssse3 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8671,8 +9139,9 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 38 08</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 38 08</opc>
+ <opr>V H W</opr>
+ <cpuid>ssse3 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8685,8 +9154,9 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 38 0a</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 38 0a</opc>
+ <opr>V H W</opr>
+ <cpuid>ssse3 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8699,8 +9169,9 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 38 09</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 38 09</opc>
+ <opr>V H W</opr>
+ <cpuid>ssse3 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8713,8 +9184,9 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 38 0b</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 38 0b</opc>
+ <opr>V H W</opr>
+ <cpuid>ssse3 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8727,8 +9199,9 @@
</span><span class="cx"> </def>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 3a 0f</opc>
- <opr>V W Ib</opr>
</del><ins>+ <opc>/sse=66 0f 3a 0f</opc>
+ <opr>V H W Ib</opr>
+ <cpuid>ssse3 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8740,8 +9213,9 @@
</span><span class="cx"> <mnemonic>pblendvb</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 38 10</opc>
</del><ins>+ <opc>/sse=66 0f 38 10</opc>
</ins><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>sse4.1</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8749,8 +9223,9 @@
</span><span class="cx"> <mnemonic>pmuldq</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 38 28</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 38 28</opc>
+ <opr>V H W</opr>
+ <cpuid>sse4.1 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8758,8 +9233,9 @@
</span><span class="cx"> <mnemonic>pminsb</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 38 38</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 38 38</opc>
+ <opr>V H W</opr>
+ <cpuid>sse4.1 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8767,8 +9243,9 @@
</span><span class="cx"> <mnemonic>pminsd</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 38 39</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 38 39</opc>
+ <opr>V H W</opr>
+ <cpuid>sse4.1 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8776,8 +9253,9 @@
</span><span class="cx"> <mnemonic>pminuw</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 38 3a</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 38 3a</opc>
+ <opr>V H W</opr>
+ <cpuid>sse4.1 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8785,8 +9263,9 @@
</span><span class="cx"> <mnemonic>pminud</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 38 3b</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 38 3b</opc>
+ <opr>V H W</opr>
+ <cpuid>sse4.1 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8794,8 +9273,9 @@
</span><span class="cx"> <mnemonic>pmaxsb</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 38 3c</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 38 3c</opc>
+ <opr>V H W</opr>
+ <cpuid>sse4.1 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8803,8 +9283,9 @@
</span><span class="cx"> <mnemonic>pmaxsd</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 38 3d</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 38 3d</opc>
+ <opr>V H W</opr>
+ <cpuid>sse4.1 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8812,17 +9293,29 @@
</span><span class="cx"> <mnemonic>pmaxud</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 38 3f</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 38 3f</opc>
+ <opr>V H W</opr>
+ <cpuid>sse4.1 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><ins>+ <mnemonic>pmaxuw</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb</pfx>
+ <opc>/sse=66 0f 38 3e</opc>
+ <opr>V H W</opr>
+ <cpuid>sse4.1 avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
</ins><span class="cx"> <mnemonic>pmulld</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 38 40</opc>
- <opr>V W</opr>
</del><ins>+ <opc>/sse=66 0f 38 40</opc>
+ <opr>V H W</opr>
+ <cpuid>sse4.1 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8830,26 +9323,29 @@
</span><span class="cx"> <mnemonic>phminposuw</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 38 41</opc>
</del><ins>+ <opc>/sse=66 0f 38 41</opc>
</ins><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>sse4.1 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>roundps</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 3a 08</opc>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 3a 08</opc>
</ins><span class="cx"> <opr>V W Ib</opr>
</span><ins>+ <cpuid>sse avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>roundpd</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 3a 09</opc>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 3a 09</opc>
</ins><span class="cx"> <opr>V W Ib</opr>
</span><ins>+ <cpuid>sse4.1 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8857,8 +9353,9 @@
</span><span class="cx"> <mnemonic>roundss</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 3a 0a</opc>
- <opr>V W Ib</opr>
</del><ins>+ <opc>/sse=66 0f 3a 0a</opc>
+ <opr>V H W Ib</opr>
+ <cpuid>sse4.1 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="lines">@@ -8866,94 +9363,737 @@
</span><span class="cx"> <mnemonic>roundsd</mnemonic>
</span><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 3a 0b</opc>
- <opr>V W Ib</opr>
</del><ins>+ <opc>/sse=66 0f 3a 0b</opc>
+ <opr>V H W Ib</opr>
+ <cpuid>sse4.1 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><span class="cx"> <mnemonic>blendpd</mnemonic>
</span><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 3a 0d</opc>
- <opr>V W Ib</opr>
</del><ins>+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 3a 0d</opc>
+ <opr>V H W Ib</opr>
+ <cpuid>sse4.1 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><del>- <mnemonic>pblendw</mnemonic>
</del><ins>+ <mnemonic>blendps</mnemonic>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 3a 0e</opc>
- <opr>V W Ib</opr>
</del><ins>+ <opc>/sse=66 0f 3a 0c</opc>
+ <opr>V H W Ib</opr>
+ <cpuid>sse4.1 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><del>- <mnemonic>blendps</mnemonic>
</del><ins>+ <mnemonic>blendvpd</mnemonic>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 3a 0c</opc>
- <opr>V W Ib</opr>
</del><ins>+ <opc>/sse=66 0f 38 15</opc>
+ <opr>V W</opr>
+ <cpuid>sse4.1</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><del>- <mnemonic>blendvpd</mnemonic>
</del><ins>+ <mnemonic>blendvps</mnemonic>
</ins><span class="cx"> <def>
</span><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 38 15</opc>
</del><ins>+ <opc>/sse=66 0f 38 14</opc>
</ins><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>sse4.1</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><del>- <mnemonic>blendvps</mnemonic>
</del><ins>+ <mnemonic>bound</mnemonic>
</ins><span class="cx"> <def>
</span><ins>+ <pfx>aso oso</pfx>
+ <opc>62 /m=!64</opc>
+ <opr>Gv M</opr>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>bsf</mnemonic>
+ <def>
+ <pfx>aso oso rexw rexr rexx rexb</pfx>
+ <opc>0f bc</opc>
+ <opr>Gv Ev</opr>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>bsr</mnemonic>
+ <def>
+ <pfx>aso oso rexw rexr rexx rexb</pfx>
+ <opc>0f bd</opc>
+ <opr>Gv Ev</opr>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>bswap</mnemonic>
+ <def>
+ <pfx>oso rexw rexb</pfx>
+ <opc>0f c8</opc>
+ <opr>R0y</opr>
+ </def>
+ <def>
+ <pfx>oso rexw rexb</pfx>
+ <opc>0f c9</opc>
+ <opr>R1y</opr>
+ </def>
+ <def>
+ <pfx>oso rexw rexb</pfx>
+ <opc>0f ca</opc>
+ <opr>R2y</opr>
+ </def>
+ <def>
+ <pfx>oso rexw rexb</pfx>
+ <opc>0f cb</opc>
+ <opr>R3y</opr>
+ </def>
+ <def>
+ <pfx>oso rexw rexb</pfx>
+ <opc>0f cc</opc>
+ <opr>R4y</opr>
+ </def>
+ <def>
+ <pfx>oso rexw rexb</pfx>
+ <opc>0f cd</opc>
+ <opr>R5y</opr>
+ </def>
+ <def>
+ <pfx>oso rexw rexb</pfx>
+ <opc>0f ce</opc>
+ <opr>R6y</opr>
+ </def>
+ <def>
+ <pfx>oso rexw rexb</pfx>
+ <opc>0f cf</opc>
+ <opr>R7y</opr>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>bt</mnemonic>
+ <def>
+ <pfx>aso oso rexw rexr rexx rexb</pfx>
+ <opc>0f ba /reg=4</opc>
+ <opr>Ev Ib</opr>
+ </def>
+ <def>
+ <pfx>aso oso rexw rexr rexx rexb</pfx>
+ <opc>0f a3</opc>
+ <opr>Ev Gv</opr>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>btc</mnemonic>
+ <def>
+ <pfx>aso oso rexw rexr rexx rexb</pfx>
+ <opc>0f bb</opc>
+ <opr>Ev Gv</opr>
+ </def>
+ <def>
+ <pfx>aso oso rexw rexr rexx rexb</pfx>
+ <opc>0f ba /reg=7</opc>
+ <opr>Ev Ib</opr>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>btr</mnemonic>
+ <def>
+ <pfx>aso oso rexw rexr rexx rexb</pfx>
+ <opc>0f b3</opc>
+ <opr>Ev Gv</opr>
+ </def>
+ <def>
+ <pfx>aso oso rexw rexr rexx rexb</pfx>
+ <opc>0f ba /reg=6</opc>
+ <opr>Ev Ib</opr>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>bts</mnemonic>
+ <def>
+ <pfx>aso oso rexw rexr rexx rexb</pfx>
+ <opc>0f ab</opc>
+ <opr>Ev Gv</opr>
+ </def>
+ <def>
+ <pfx>aso oso rexw rexr rexx rexb</pfx>
+ <opc>0f ba /reg=5</opc>
+ <opr>Ev Ib</opr>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>pblendw</mnemonic>
+ <def>
</ins><span class="cx"> <pfx>aso rexr rexx rexb</pfx>
</span><del>- <opc>sse66 0f 38 14</opc>
</del><ins>+ <opc>/sse=66 0f 3a 0e</opc>
+ <opr>V H W Ib</opr>
+ <cpuid>sse4.1 avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>mpsadbw</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 3a 42</opc>
+ <opr>V H W Ib</opr>
+ <cpuid>sse4.1 avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>movntdqa</mnemonic>
+ <def>
+ <pfx>aso rexr rexw rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 38 2a</opc>
+ <opr>V M</opr>
+ <cpuid>sse4.1 avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>packusdw</mnemonic>
+ <def>
+ <pfx>aso rexr rexw rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 38 2b</opc>
+ <opr>V H W</opr>
+ <cpuid>sse2 avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>pmovsxbw</mnemonic>
+ <def>
+ <pfx>aso rexr rexw rexx rexb</pfx>
+ <opc>/sse=66 0f 38 20</opc>
+ <opr>V MqU</opr>
+ <cpuid>sse4.1 avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>pmovsxbd</mnemonic>
+ <def>
+ <pfx>aso rexr rexw rexx rexb</pfx>
+ <opc>/sse=66 0f 38 21</opc>
+ <opr>V MdU</opr>
+ <cpuid>sse4.1 avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>pmovsxbq</mnemonic>
+ <def>
+ <pfx>aso rexr rexw rexx rexb</pfx>
+ <opc>/sse=66 0f 38 22</opc>
+ <opr>V MwU</opr>
+ <cpuid>sse4.1 avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>pmovsxwd</mnemonic>
+ <def>
+ <pfx>aso rexr rexw rexx rexb</pfx>
+ <opc>/sse=66 0f 38 23</opc>
+ <opr>V MqU</opr>
+ <cpuid>sse4.1 avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>pmovsxwq</mnemonic>
+ <def>
+ <pfx>aso rexr rexw rexx rexb</pfx>
+ <opc>/sse=66 0f 38 24</opc>
+ <opr>V MdU</opr>
+ <cpuid>sse4.1 avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>pmovsxdq</mnemonic>
+ <def>
+ <pfx>aso rexr rexw rexx rexb</pfx>
+ <opc>/sse=66 0f 38 25</opc>
+ <opr>V MqU</opr>
+ <cpuid>sse4.1</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>pmovzxbw</mnemonic>
+ <def>
+ <pfx>aso rexr rexw rexx rexb</pfx>
+ <opc>/sse=66 0f 38 30</opc>
+ <opr>V MqU</opr>
+ <cpuid>sse4.1 avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>pmovzxbd</mnemonic>
+ <def>
+ <pfx>aso rexr rexw rexx rexb</pfx>
+ <opc>/sse=66 0f 38 31</opc>
+ <opr>V MdU</opr>
+ <cpuid>sse4.1 avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>pmovzxbq</mnemonic>
+ <def>
+ <pfx>aso rexr rexw rexx rexb</pfx>
+ <opc>/sse=66 0f 38 32</opc>
+ <opr>V MwU</opr>
+ <cpuid>sse4.1 avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>pmovzxwd</mnemonic>
+ <def>
+ <pfx>aso rexr rexw rexx rexb</pfx>
+ <opc>/sse=66 0f 38 33</opc>
+ <opr>V MqU</opr>
+ <cpuid>sse4.1 avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>pmovzxwq</mnemonic>
+ <def>
+ <pfx>aso rexr rexw rexx rexb</pfx>
+ <opc>/sse=66 0f 38 34</opc>
+ <opr>V MdU</opr>
+ <cpuid>sse4.1 avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>pmovzxdq</mnemonic>
+ <def>
+ <pfx>aso rexr rexw rexx rexb</pfx>
+ <opc>/sse=66 0f 38 35</opc>
+ <opr>V MqU</opr>
+ <cpuid>sse4.1 avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>pcmpeqq</mnemonic>
+ <def>
+ <pfx>aso rexr rexw rexx rexb</pfx>
+ <opc>/sse=66 0f 38 29</opc>
+ <opr>V H W</opr>
+ <cpuid>sse4.1 avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>popcnt</mnemonic>
+ <def>
+ <pfx>aso oso rexr rexw rexx rexb</pfx>
+ <opc>/sse=f3 0f b8</opc>
+ <opr>Gv Ev</opr>
+ </def>
+ <cpuid>sse4.2</cpuid>
+ </instruction>
+
+ <instruction>
+ <mnemonic>ptest</mnemonic>
+ <def>
+ <pfx>aso rexr rexw rexx rexb vexl</pfx>
+ <opc>/sse=66 0f 38 17</opc>
</ins><span class="cx"> <opr>V W</opr>
</span><ins>+ <cpuid>sse4.1 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><del>- <mnemonic>dpps</mnemonic>
</del><ins>+ <mnemonic>pcmpestri</mnemonic>
</ins><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 3a 40</opc>
</del><ins>+ <pfx>aso rexr rexw rexx rexb</pfx>
+ <opc>/sse=66 0f 3a 61</opc>
</ins><span class="cx"> <opr>V W Ib</opr>
</span><ins>+ <cpuid>sse4.2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><del>- <mnemonic>dppd</mnemonic>
</del><ins>+ <mnemonic>pcmpestrm</mnemonic>
</ins><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 3a 41</opc>
</del><ins>+ <pfx>aso rexr rexw rexx rexb</pfx>
+ <opc>/sse=66 0f 3a 60</opc>
</ins><span class="cx"> <opr>V W Ib</opr>
</span><ins>+ <cpuid>sse4.2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><del>- <mnemonic>mpsadbw</mnemonic>
</del><ins>+ <mnemonic>pcmpgtq</mnemonic>
</ins><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexx rexb</pfx>
- <opc>sse66 0f 3a 42</opc>
</del><ins>+ <pfx>aso rexr rexw rexx rexb</pfx>
+ <opc>/sse=66 0f 38 37</opc>
+ <opr>V H W</opr>
+ <cpuid>sse4.2 avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>pcmpistri</mnemonic>
+ <def>
+ <pfx>aso rexr rexw rexx rexb</pfx>
+ <opc>/sse=66 0f 3a 63</opc>
</ins><span class="cx"> <opr>V W Ib</opr>
</span><ins>+ <cpuid>sse4.2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><del>- <mnemonic>extractps</mnemonic>
</del><ins>+ <mnemonic>pcmpistrm</mnemonic>
</ins><span class="cx"> <def>
</span><del>- <pfx>aso rexr rexw rexb</pfx>
- <opc>sse66 0f 3a 17</opc>
- <opr>MdRy V Ib</opr>
</del><ins>+ <pfx>aso rexr rexw rexx rexb</pfx>
+ <opc>/sse=66 0f 3a 62</opc>
+ <opr>V W Ib</opr>
+ <cpuid>sse4.2 avx</cpuid>
</ins><span class="cx"> </def>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><span class="cx"> <instruction>
</span><ins>+ <mnemonic>movbe</mnemonic>
+ <def>
+ <pfx>aso oso rexr rexw rexx rexb</pfx>
+ <opc>0f 38 f0</opc>
+ <opr>Gv Mv</opr>
+ <cpuid>sse3 atom</cpuid>
+ </def>
+ <def>
+ <pfx>aso oso rexr rexw rexx rexb</pfx>
+ <opc>0f 38 f1</opc>
+ <opr>Mv Gv</opr>
+ <cpuid>sse3 atom</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>crc32</mnemonic>
+ <def>
+ <pfx>aso oso rexr rexw rexx rexb</pfx>
+ <opc>/sse=f2 0f 38 f0</opc>
+ <opr>Gy Eb</opr>
+ <cpuid>sse4.2</cpuid>
+ </def>
+ <def>
+ <pfx>aso oso rexr rexw rexx rexb</pfx>
+ <opc>/sse=f2 0f 38 f1</opc>
+ <opr>Gy Ev</opr>
+ <cpuid>sse4.2</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
</ins><span class="cx"> <mnemonic>invalid</mnemonic>
</span><span class="cx"> </instruction>
</span><span class="cx">
</span><ins>+ <instruction>
+ <mnemonic>vbroadcastss</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/vex=66_0f38 18 /vexw=0</opc>
+ <opr>V Md</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>vbroadcastsd</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/vex=66_0f38 19 /vexw=0 /vexl=1</opc>
+ <opr>Vqq Mq</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>vextractf128</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/vex=66_0f3a 19 /vexw=0 /vexl=1</opc>
+ <opr>Wdq Vqq Ib</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>vinsertf128</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/vex=66_0f3a 18 /vexw=0 /vexl=1</opc>
+ <opr>Vqq Hqq Wdq Ib</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>vmaskmovps</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/vex=66_0f38 2c /vexw=0</opc>
+ <opr>V H M</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ <def>
+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/vex=66_0f38 2e /vexw=0</opc>
+ <opr>M H V</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>vmaskmovpd</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/vex=66_0f38 2d /vexw=0</opc>
+ <opr>V H M</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ <def>
+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/vex=66_0f38 2f /vexw=0</opc>
+ <opr>M H V</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>vpermilpd</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/vex=66_0f38 0d /vexw=0</opc>
+ <opr>Vx Hx Wx</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ <def>
+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/vex=66_0f3a 05 /vexw=0</opc>
+ <opr>V W Ib</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>vpermilps</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/vex=66_0f38 0c /vexw=0</opc>
+ <opr>Vx Hx Wx</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ <def>
+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/vex=66_0f3a 04 /vexw=0</opc>
+ <opr>Vx Wx Ib</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>vperm2f128</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/vex=66_0f3a 06 /vexw=0 /vexl=1</opc>
+ <opr>Vqq Hqq Wqq Ib</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>vtestps</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/vex=66_0f38 0e /vexw=0</opc>
+ <opr>Vx Wx</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>vtestpd</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/vex=66_0f38 0f /vexw=0</opc>
+ <opr>Vx Wx</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>vzeroupper</mnemonic>
+ <def>
+ <opc>/vex=0f 77 /vexl=0</opc>
+ <cpuid>avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>vzeroall</mnemonic>
+ <def>
+ <opc>/vex=0f 77 /vexl=1</opc>
+ <cpuid>avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>vblendvpd</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/vex=66_0f3a 4b /vexw=0</opc>
+ <opr>Vx Hx Wx Lx</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>vblendvps</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb vexl</pfx>
+ <opc>/vex=66_0f3a 4a /vexw=0</opc>
+ <opr>Vx Hx Wx Lx</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>vmovsd</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb</pfx>
+ <opc>/vex=f2_0f 10 /mod=11</opc>
+ <opr>V H U</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ <def>
+ <pfx>aso rexr rexx rexb</pfx>
+ <opc>/vex=f2_0f 10 /mod=!11</opc>
+ <opr>V Mq</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ <def>
+ <pfx>aso rexr rexx rexb</pfx>
+ <opc>/vex=f2_0f 11 /mod=11</opc>
+ <opr>U H V</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ <def>
+ <pfx>aso rexr rexx rexb</pfx>
+ <opc>/vex=f2_0f 11 /mod=!11</opc>
+ <opr>Mq V</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>vmovss</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb</pfx>
+ <opc>/vex=f3_0f 10 /mod=11</opc>
+ <opr>V H U</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ <def>
+ <pfx>aso rexr rexx rexb</pfx>
+ <opc>/vex=f3_0f 10 /mod=!11</opc>
+ <opr>V Md</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ <def>
+ <pfx>aso rexr rexx rexb</pfx>
+ <opc>/vex=f3_0f 11 /mod=11</opc>
+ <opr>U H V</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ <def>
+ <pfx>aso rexr rexx rexb</pfx>
+ <opc>/vex=f3_0f 11 /mod=!11</opc>
+ <opr>Md V</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>vpblendvb</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb</pfx>
+ <opc>/vex=66_0f3a 4c /vexw=0</opc>
+ <opr>V H W L</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>vpsllw</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb</pfx>
+ <opc>/vex=66_0f f1 /vexl=0</opc>
+ <opr>V H W</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ <def>
+ <pfx>aso rexr rexx rexb</pfx>
+ <opc>/vex=66_0f 71 /reg=6 /vexl=0</opc>
+ <opr>H V W</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>vpslld</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb</pfx>
+ <opc>/vex=66_0f f2 /vexl=0</opc>
+ <opr>V H W</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ <def>
+ <pfx>aso rexr rexx rexb</pfx>
+ <opc>/vex=66_0f 72 /reg=6 /vexl=0</opc>
+ <opr>H V W</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ </instruction>
+
+ <instruction>
+ <mnemonic>vpsllq</mnemonic>
+ <def>
+ <pfx>aso rexr rexx rexb</pfx>
+ <opc>/vex=66_0f f3 /vexl=0</opc>
+ <opr>V H W</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ <def>
+ <pfx>aso rexr rexx rexb</pfx>
+ <opc>/vex=66_0f 73 /reg=6 /vexl=0</opc>
+ <opr>H V W</opr>
+ <cpuid>avx</cpuid>
+ </def>
+ </instruction>
+
</ins><span class="cx"> </x86optable>
</span></span></pre></div>
<a id="trunkSourceJavaScriptCoredisassemblerudis86ud_itabpy"></a>
<div class="addfile"><h4>Added: trunk/Source/JavaScriptCore/disassembler/udis86/ud_itab.py (0 => 198832)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/disassembler/udis86/ud_itab.py (rev 0)
+++ trunk/Source/JavaScriptCore/disassembler/udis86/ud_itab.py 2016-03-30 07:17:14 UTC (rev 198832)
</span><span class="lines">@@ -0,0 +1,379 @@
</span><ins>+# udis86 - scripts/ud_itab.py
+#
+# Copyright (c) 2009, 2013 Vivek Thampi
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import os
+import sys
+from ud_opcode import UdOpcodeTable, UdOpcodeTables, UdInsnDef
+
+class UdItabGenerator:
+
+ OperandDict = {
+ "Av" : [ "OP_A" , "SZ_V" ],
+ "E" : [ "OP_E" , "SZ_NA" ],
+ "Eb" : [ "OP_E" , "SZ_B" ],
+ "Ew" : [ "OP_E" , "SZ_W" ],
+ "Ev" : [ "OP_E" , "SZ_V" ],
+ "Ed" : [ "OP_E" , "SZ_D" ],
+ "Ey" : [ "OP_E" , "SZ_Y" ],
+ "Eq" : [ "OP_E" , "SZ_Q" ],
+ "Ez" : [ "OP_E" , "SZ_Z" ],
+ "Fv" : [ "OP_F" , "SZ_V" ],
+ "G" : [ "OP_G" , "SZ_NA" ],
+ "Gb" : [ "OP_G" , "SZ_B" ],
+ "Gw" : [ "OP_G" , "SZ_W" ],
+ "Gv" : [ "OP_G" , "SZ_V" ],
+ "Gy" : [ "OP_G" , "SZ_Y" ],
+ "Gd" : [ "OP_G" , "SZ_D" ],
+ "Gq" : [ "OP_G" , "SZ_Q" ],
+ "Gz" : [ "OP_G" , "SZ_Z" ],
+ "M" : [ "OP_M" , "SZ_NA" ],
+ "Mb" : [ "OP_M" , "SZ_B" ],
+ "Mw" : [ "OP_M" , "SZ_W" ],
+ "Ms" : [ "OP_M" , "SZ_W" ],
+ "Md" : [ "OP_M" , "SZ_D" ],
+ "Mq" : [ "OP_M" , "SZ_Q" ],
+ "Mdq" : [ "OP_M" , "SZ_DQ" ],
+ "Mv" : [ "OP_M" , "SZ_V" ],
+ "Mt" : [ "OP_M" , "SZ_T" ],
+ "Mo" : [ "OP_M" , "SZ_O" ],
+ "MbRd" : [ "OP_MR" , "SZ_BD" ],
+ "MbRv" : [ "OP_MR" , "SZ_BV" ],
+ "MwRv" : [ "OP_MR" , "SZ_WV" ],
+ "MwRd" : [ "OP_MR" , "SZ_WD" ],
+ "MwRy" : [ "OP_MR" , "SZ_WY" ],
+ "MdRy" : [ "OP_MR" , "SZ_DY" ],
+ "I1" : [ "OP_I1" , "SZ_NA" ],
+ "I3" : [ "OP_I3" , "SZ_NA" ],
+ "Ib" : [ "OP_I" , "SZ_B" ],
+ "Iw" : [ "OP_I" , "SZ_W" ],
+ "Iv" : [ "OP_I" , "SZ_V" ],
+ "Iz" : [ "OP_I" , "SZ_Z" ],
+ "sIb" : [ "OP_sI" , "SZ_B" ],
+ "sIz" : [ "OP_sI" , "SZ_Z" ],
+ "sIv" : [ "OP_sI" , "SZ_V" ],
+ "Jv" : [ "OP_J" , "SZ_V" ],
+ "Jz" : [ "OP_J" , "SZ_Z" ],
+ "Jb" : [ "OP_J" , "SZ_B" ],
+ "R" : [ "OP_R" , "SZ_RDQ" ],
+ "C" : [ "OP_C" , "SZ_NA" ],
+ "D" : [ "OP_D" , "SZ_NA" ],
+ "S" : [ "OP_S" , "SZ_W" ],
+ "Ob" : [ "OP_O" , "SZ_B" ],
+ "Ow" : [ "OP_O" , "SZ_W" ],
+ "Ov" : [ "OP_O" , "SZ_V" ],
+ "U" : [ "OP_U" , "SZ_O" ],
+ "Ux" : [ "OP_U" , "SZ_X" ],
+ "V" : [ "OP_V" , "SZ_DQ" ],
+ "Vdq" : [ "OP_V" , "SZ_DQ" ],
+ "Vqq" : [ "OP_V" , "SZ_QQ" ],
+ "Vsd" : [ "OP_V" , "SZ_Q" ],
+ "Vx" : [ "OP_V" , "SZ_X" ],
+ "H" : [ "OP_H" , "SZ_X" ],
+ "Hx" : [ "OP_H" , "SZ_X" ],
+ "Hqq" : [ "OP_H" , "SZ_QQ" ],
+ "W" : [ "OP_W" , "SZ_DQ" ],
+ "Wdq" : [ "OP_W" , "SZ_DQ" ],
+ "Wqq" : [ "OP_W" , "SZ_QQ" ],
+ "Wsd" : [ "OP_W" , "SZ_Q" ],
+ "Wx" : [ "OP_W" , "SZ_X" ],
+ "L" : [ "OP_L" , "SZ_O" ],
+ "Lx" : [ "OP_L" , "SZ_X" ],
+ "MwU" : [ "OP_MU" , "SZ_WO" ],
+ "MdU" : [ "OP_MU" , "SZ_DO" ],
+ "MqU" : [ "OP_MU" , "SZ_QO" ],
+ "N" : [ "OP_N" , "SZ_Q" ],
+ "P" : [ "OP_P" , "SZ_Q" ],
+ "Q" : [ "OP_Q" , "SZ_Q" ],
+ "AL" : [ "OP_AL" , "SZ_B" ],
+ "AX" : [ "OP_AX" , "SZ_W" ],
+ "eAX" : [ "OP_eAX" , "SZ_Z" ],
+ "rAX" : [ "OP_rAX" , "SZ_V" ],
+ "CL" : [ "OP_CL" , "SZ_B" ],
+ "CX" : [ "OP_CX" , "SZ_W" ],
+ "eCX" : [ "OP_eCX" , "SZ_Z" ],
+ "rCX" : [ "OP_rCX" , "SZ_V" ],
+ "DL" : [ "OP_DL" , "SZ_B" ],
+ "DX" : [ "OP_DX" , "SZ_W" ],
+ "eDX" : [ "OP_eDX" , "SZ_Z" ],
+ "rDX" : [ "OP_rDX" , "SZ_V" ],
+ "R0b" : [ "OP_R0" , "SZ_B" ],
+ "R1b" : [ "OP_R1" , "SZ_B" ],
+ "R2b" : [ "OP_R2" , "SZ_B" ],
+ "R3b" : [ "OP_R3" , "SZ_B" ],
+ "R4b" : [ "OP_R4" , "SZ_B" ],
+ "R5b" : [ "OP_R5" , "SZ_B" ],
+ "R6b" : [ "OP_R6" , "SZ_B" ],
+ "R7b" : [ "OP_R7" , "SZ_B" ],
+ "R0w" : [ "OP_R0" , "SZ_W" ],
+ "R1w" : [ "OP_R1" , "SZ_W" ],
+ "R2w" : [ "OP_R2" , "SZ_W" ],
+ "R3w" : [ "OP_R3" , "SZ_W" ],
+ "R4w" : [ "OP_R4" , "SZ_W" ],
+ "R5w" : [ "OP_R5" , "SZ_W" ],
+ "R6w" : [ "OP_R6" , "SZ_W" ],
+ "R7w" : [ "OP_R7" , "SZ_W" ],
+ "R0v" : [ "OP_R0" , "SZ_V" ],
+ "R1v" : [ "OP_R1" , "SZ_V" ],
+ "R2v" : [ "OP_R2" , "SZ_V" ],
+ "R3v" : [ "OP_R3" , "SZ_V" ],
+ "R4v" : [ "OP_R4" , "SZ_V" ],
+ "R5v" : [ "OP_R5" , "SZ_V" ],
+ "R6v" : [ "OP_R6" , "SZ_V" ],
+ "R7v" : [ "OP_R7" , "SZ_V" ],
+ "R0z" : [ "OP_R0" , "SZ_Z" ],
+ "R1z" : [ "OP_R1" , "SZ_Z" ],
+ "R2z" : [ "OP_R2" , "SZ_Z" ],
+ "R3z" : [ "OP_R3" , "SZ_Z" ],
+ "R4z" : [ "OP_R4" , "SZ_Z" ],
+ "R5z" : [ "OP_R5" , "SZ_Z" ],
+ "R6z" : [ "OP_R6" , "SZ_Z" ],
+ "R7z" : [ "OP_R7" , "SZ_Z" ],
+ "R0y" : [ "OP_R0" , "SZ_Y" ],
+ "R1y" : [ "OP_R1" , "SZ_Y" ],
+ "R2y" : [ "OP_R2" , "SZ_Y" ],
+ "R3y" : [ "OP_R3" , "SZ_Y" ],
+ "R4y" : [ "OP_R4" , "SZ_Y" ],
+ "R5y" : [ "OP_R5" , "SZ_Y" ],
+ "R6y" : [ "OP_R6" , "SZ_Y" ],
+ "R7y" : [ "OP_R7" , "SZ_Y" ],
+ "ES" : [ "OP_ES" , "SZ_NA" ],
+ "CS" : [ "OP_CS" , "SZ_NA" ],
+ "DS" : [ "OP_DS" , "SZ_NA" ],
+ "SS" : [ "OP_SS" , "SZ_NA" ],
+ "GS" : [ "OP_GS" , "SZ_NA" ],
+ "FS" : [ "OP_FS" , "SZ_NA" ],
+ "ST0" : [ "OP_ST0" , "SZ_NA" ],
+ "ST1" : [ "OP_ST1" , "SZ_NA" ],
+ "ST2" : [ "OP_ST2" , "SZ_NA" ],
+ "ST3" : [ "OP_ST3" , "SZ_NA" ],
+ "ST4" : [ "OP_ST4" , "SZ_NA" ],
+ "ST5" : [ "OP_ST5" , "SZ_NA" ],
+ "ST6" : [ "OP_ST6" , "SZ_NA" ],
+ "ST7" : [ "OP_ST7" , "SZ_NA" ],
+ "NONE" : [ "OP_NONE" , "SZ_NA" ],
+ }
+
+ #
+ # opcode prefix dictionary
+ #
+ PrefixDict = {
+ "rep" : "P_str",
+ "repz" : "P_strz",
+ "aso" : "P_aso",
+ "oso" : "P_oso",
+ "rexw" : "P_rexw",
+ "rexb" : "P_rexb",
+ "rexx" : "P_rexx",
+ "rexr" : "P_rexr",
+ "vexl" : "P_vexl",
+ "vexw" : "P_vexw",
+ "seg" : "P_seg",
+ "inv64" : "P_inv64",
+ "def64" : "P_def64",
+ "cast" : "P_cast",
+ }
+
+ MnemonicAliases = ( "invalid", "3dnow", "none", "db", "pause" )
+
+ def __init__(self, tables):
+ self.tables = tables
+ self._insnIndexMap, i = {}, 0
+ for insn in tables.getInsnList():
+ self._insnIndexMap[insn], i = i, i + 1
+
+ self._tableIndexMap, i = {}, 0
+ for table in tables.getTableList():
+ self._tableIndexMap[table], i = i, i + 1
+
+ def getInsnIndex(self, insn):
+ assert isinstance(insn, UdInsnDef)
+ return self._insnIndexMap[insn]
+
+ def getTableIndex(self, table):
+ assert isinstance(table, UdOpcodeTable)
+ return self._tableIndexMap[table]
+
+ def getTableName(self, table):
+ return "ud_itab__%d" % self.getTableIndex(table)
+
+ def genOpcodeTable(self, table, isGlobal=False):
+ """Emit Opcode Table in C.
+ """
+ self.ItabC.write( "\n" );
+ if not isGlobal:
+ self.ItabC.write('static ')
+ self.ItabC.write( "const uint16_t %s[] = {\n" % self.getTableName(table))
+ for i in range(table.size()):
+ if i > 0 and i % 4 == 0:
+ self.ItabC.write( "\n" )
+ if i % 4 == 0:
+ self.ItabC.write( " /* %2x */" % i)
+ e = table.entryAt(i)
+ if e is None:
+ self.ItabC.write("%12s," % "INVALID")
+ elif isinstance(e, UdOpcodeTable):
+ self.ItabC.write("%12s," % ("GROUP(%d)" % self.getTableIndex(e)))
+ elif isinstance(e, UdInsnDef):
+ self.ItabC.write("%12s," % self.getInsnIndex(e))
+ self.ItabC.write( "\n" )
+ self.ItabC.write( "};\n" )
+
+
+ def genOpcodeTables(self):
+ tables = self.tables.getTableList()
+ for table in tables:
+ self.genOpcodeTable(table, table is self.tables.root)
+
+
+ def genOpcodeTablesLookupIndex(self):
+ self.ItabC.write( "\n\n" );
+ self.ItabC.write( "struct ud_lookup_table_list_entry ud_lookup_table_list[] = {\n" )
+ for table in self.tables.getTableList():
+ f0 = self.getTableName(table) + ","
+ f1 = table.label() + ","
+ f2 = "\"%s\"" % table.meta()
+ self.ItabC.write(" /* %03d */ { %s %s %s },\n" %
+ (self.getTableIndex(table), f0, f1, f2))
+ self.ItabC.write( "};" )
+
+
+ def genInsnTable( self ):
+ self.ItabC.write( "struct ud_itab_entry ud_itab[] = {\n" );
+ for insn in self.tables.getInsnList():
+ opr_c = [ "O_NONE", "O_NONE", "O_NONE", "O_NONE" ]
+ pfx_c = []
+ opr = insn.operands
+ for i in range(len(opr)):
+ if not (opr[i] in self.OperandDict.keys()):
+ print("error: invalid operand declaration: %s\n" % opr[i])
+ opr_c[i] = "O_" + opr[i]
+ opr = "%s %s %s %s" % (opr_c[0] + ",", opr_c[1] + ",",
+ opr_c[2] + ",", opr_c[3])
+
+ for p in insn.prefixes:
+ if not ( p in self.PrefixDict.keys() ):
+ print("error: invalid prefix specification: %s \n" % pfx)
+ pfx_c.append( self.PrefixDict[p] )
+ if len(insn.prefixes) == 0:
+ pfx_c.append( "P_none" )
+ pfx = "|".join( pfx_c )
+
+ self.ItabC.write( " /* %04d */ { UD_I%s %s, %s },\n" \
+ % ( self.getInsnIndex(insn), insn.mnemonic + ',', opr, pfx ) )
+ self.ItabC.write( "};\n" )
+
+
+ def getMnemonicsList(self):
+ mnemonics = self.tables.getMnemonicsList()
+ mnemonics.extend(self.MnemonicAliases)
+ return mnemonics
+
+ def genMnemonicsList(self):
+ mnemonics = self.getMnemonicsList()
+ self.ItabC.write( "\n\n" );
+ self.ItabC.write( "const char* ud_mnemonics_str[] = {\n " )
+ self.ItabC.write( ",\n ".join( [ "\"%s\"" % m for m in mnemonics ] ) )
+ self.ItabC.write( "\n};\n" )
+
+
+ def genItabH( self, filePath ):
+ self.ItabH = open( filePath, "w" )
+
+ # Generate Table Type Enumeration
+ self.ItabH.write( "#ifndef UD_ITAB_H\n" )
+ self.ItabH.write( "#define UD_ITAB_H\n\n" )
+
+ self.ItabH.write("/* itab.h -- generated by udis86:scripts/ud_itab.py, do no edit */\n\n")
+
+ # table type enumeration
+ self.ItabH.write( "/* ud_table_type -- lookup table types (see decode.c) */\n" )
+ self.ItabH.write( "enum ud_table_type {\n " )
+ enum = UdOpcodeTable.getLabels()
+ self.ItabH.write( ",\n ".join( enum ) )
+ self.ItabH.write( "\n};\n\n" );
+
+ # mnemonic enumeration
+ self.ItabH.write( "/* ud_mnemonic -- mnemonic constants */\n" )
+ enum = "enum ud_mnemonic_code {\n "
+ enum += ",\n ".join( [ "UD_I%s" % m for m in self.getMnemonicsList() ] )
+ enum += ",\n UD_MAX_MNEMONIC_CODE"
+ enum += "\n};\n"
+ self.ItabH.write( enum )
+ self.ItabH.write( "\n" )
+
+ self.ItabH.write( "extern const char * ud_mnemonics_str[];\n" )
+
+ self.ItabH.write( "\n#endif /* UD_ITAB_H */\n" )
+
+ self.ItabH.close()
+
+
+ def genItabC(self, filePath):
+ self.ItabC = open(filePath, "w")
+ self.ItabC.write("/* itab.c -- generated by udis86:scripts/ud_itab.py, do no edit")
+ self.ItabC.write(" */\n");
+ self.ItabC.write("#include \"udis86_decode.h\"\n\n");
+
+ self.ItabC.write("#define GROUP(n) (0x8000 | (n))\n")
+ self.ItabC.write("#define INVALID %d\n\n" % self.getInsnIndex(self.tables.invalidInsn))
+
+ self.genOpcodeTables()
+ self.genOpcodeTablesLookupIndex()
+
+ #
+ # Macros defining short-names for operands
+ #
+ self.ItabC.write("\n\n/* itab entry operand definitions (for readability) */\n");
+ operands = self.OperandDict.keys()
+ operands = sorted(operands)
+ for o in operands:
+ self.ItabC.write("#define O_%-7s { %-12s %-8s }\n" %
+ (o, self.OperandDict[o][0] + ",", self.OperandDict[o][1]));
+ self.ItabC.write("\n");
+
+ self.genInsnTable()
+ self.genMnemonicsList()
+
+ self.ItabC.close()
+
+ def genItab( self, location ):
+ self.genItabC(os.path.join(location, "udis86_itab.c"))
+ self.genItabH(os.path.join(location, "udis86_itab.h"))
+
+def usage():
+ print("usage: ud_itab.py <optable.xml> <output-path>")
+
+def main():
+
+ if len(sys.argv) != 3:
+ usage()
+ sys.exit(1)
+
+ tables = UdOpcodeTables(xml=sys.argv[1])
+ itab = UdItabGenerator(tables)
+ itab.genItab(sys.argv[2])
+
+if __name__ == '__main__':
+ main()
</ins></span></pre></div>
<a id="trunkSourceJavaScriptCoredisassemblerudis86ud_opcodepy"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/disassembler/udis86/ud_opcode.py (198831 => 198832)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/disassembler/udis86/ud_opcode.py 2016-03-30 07:14:10 UTC (rev 198831)
+++ trunk/Source/JavaScriptCore/disassembler/udis86/ud_opcode.py 2016-03-30 07:17:14 UTC (rev 198832)
</span><span class="lines">@@ -1,6 +1,6 @@
</span><span class="cx"> # udis86 - scripts/ud_opcode.py
</span><span class="cx"> #
</span><del>-# Copyright (c) 2009 Vivek Thampi
</del><ins>+# Copyright (c) 2009, 2013 Vivek Thampi
</ins><span class="cx"> # All rights reserved.
</span><span class="cx"> #
</span><span class="cx"> # Redistribution and use in source and binary forms, with or without modification,
</span><span class="lines">@@ -23,213 +23,600 @@
</span><span class="cx"> # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
</span><span class="cx"> # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
</span><span class="cx">
</span><del>-class UdOpcodeTables:
</del><ins>+import os
</ins><span class="cx">
</span><del>- TableInfo = {
- 'opctbl' : { 'name' : 'UD_TAB__OPC_TABLE', 'size' : 256 },
- '/sse' : { 'name' : 'UD_TAB__OPC_SSE', 'size' : 4 },
- '/reg' : { 'name' : 'UD_TAB__OPC_REG', 'size' : 8 },
- '/rm' : { 'name' : 'UD_TAB__OPC_RM', 'size' : 8 },
- '/mod' : { 'name' : 'UD_TAB__OPC_MOD', 'size' : 2 },
- '/m' : { 'name' : 'UD_TAB__OPC_MODE', 'size' : 3 },
- '/x87' : { 'name' : 'UD_TAB__OPC_X87', 'size' : 64 },
- '/a' : { 'name' : 'UD_TAB__OPC_ASIZE', 'size' : 3 },
- '/o' : { 'name' : 'UD_TAB__OPC_OSIZE', 'size' : 3 },
- '/3dnow' : { 'name' : 'UD_TAB__OPC_3DNOW', 'size' : 256 },
- 'vendor' : { 'name' : 'UD_TAB__OPC_VENDOR', 'size' : 3 },
- }
</del><ins>+# Some compatibility stuff for supporting python 2.x as well as python 3.x
+def itemslist(dict):
+ try:
+ return dict.iteritems() # python 2.x
+ except AttributeError:
+ return list(dict.items()) # python 3.x
</ins><span class="cx">
</span><del>- OpcodeTable0 = {
- 'type' : 'opctbl',
- 'entries' : {},
- 'meta' : 'table0'
- }
</del><ins>+class UdInsnDef:
+ """An x86 instruction definition
+ """
+ def __init__(self, **insnDef):
+ self.mnemonic = insnDef['mnemonic']
+ self.prefixes = insnDef['prefixes']
+ self.opcodes = insnDef['opcodes']
+ self.operands = insnDef['operands']
+ self._cpuid = insnDef['cpuid']
+ self._opcexts = {}
</ins><span class="cx">
</span><del>- OpcExtIndex = {
</del><ins>+ for opc in self.opcodes:
+ if opc.startswith('/'):
+ e, v = opc.split('=')
+ self._opcexts[e] = v
</ins><span class="cx">
</span><del>- # ssef2, ssef3, sse66
- 'sse': {
- 'none' : '00',
- 'f2' : '01',
- 'f3' : '02',
- '66' : '03'
- },
</del><ins>+ def lookupPrefix(self, pfx):
+ """Lookup prefix (if any, None otherwise), by name"""
+ return True if pfx in self.prefixes else None
</ins><span class="cx">
</span><del>- # /mod=
- 'mod': {
- '!11' : '00',
- '11' : '01'
- },
</del><span class="cx">
</span><del>- # /m=, /o=, /a=
- 'mode': {
- '16' : '00',
- '32' : '01',
- '64' : '02'
- },
</del><ins>+ @property
+ def vendor(self):
+ return self._opcexts.get('/vendor', None)
</ins><span class="cx">
</span><del>- 'vendor' : {
- 'amd' : '00',
- 'intel' : '01',
- 'any' : '02'
</del><ins>+ @property
+ def mode(self):
+ return self._opcexts.get('/m', None)
+
+ @property
+ def osize(self):
+ return self._opcexts.get('/o', None)
+
+ def isDef64(self):
+ return 'def64' in self.prefixes
+
+ def __str__(self):
+ return self.mnemonic + " " + ', '.join(self.operands) + \
+ " " + ' '.join(self.opcodes)
+
+
+class UdOpcodeTable:
+ """A single table of instruction definitions, indexed by
+ a decode field.
+ """
+
+ class CollisionError(Exception):
+ pass
+
+ class IndexError(Exception):
+ """Invalid Index Error"""
+ pass
+
+ @classmethod
+ def vendor2idx(cls, v):
+ return (0 if v == 'amd'
+ else (1 if v == 'intel'
+ else 2))
+
+ @classmethod
+ def vex2idx(cls, v):
+ if v.startswith("none_"):
+ v = v[5:]
+ vexOpcExtMap = {
+ 'none' : 0x0,
+ '0f' : 0x1,
+ '0f38' : 0x2,
+ '0f3a' : 0x3,
+ '66' : 0x4,
+ '66_0f' : 0x5,
+ '66_0f38' : 0x6,
+ '66_0f3a' : 0x7,
+ 'f3' : 0x8,
+ 'f3_0f' : 0x9,
+ 'f3_0f38' : 0xa,
+ 'f3_0f3a' : 0xb,
+ 'f2' : 0xc,
+ 'f2_0f' : 0xd,
+ 'f2_0f38' : 0xe,
+ 'f2_0f3a' : 0xf,
</ins><span class="cx"> }
</span><ins>+ return vexOpcExtMap[v]
+
+
+ # A mapping of opcode extensions to their representational
+ # values used in the opcode map.
+ OpcExtMap = {
+ '/rm' : lambda v: int(v, 16),
+ '/x87' : lambda v: int(v, 16),
+ '/3dnow' : lambda v: int(v, 16),
+ '/reg' : lambda v: int(v, 16),
+ # modrm.mod
+ # (!11, 11) => (00b, 01b)
+ '/mod' : lambda v: 0 if v == '!11' else 1,
+ # Mode extensions:
+ # (16, 32, 64) => (00, 01, 02)
+ '/o' : lambda v: (int(v) / 32),
+ '/a' : lambda v: (int(v) / 32),
+ # Disassembly mode
+ # (!64, 64) => (00b, 01b)
+ '/m' : lambda v: 1 if v == '64' else 0,
+ # SSE
+ # none => 0
+ # f2 => 1
+ # f3 => 2
+ # 66 => 3
+ '/sse' : lambda v: (0 if v == 'none'
+ else (((int(v, 16) & 0xf) + 1) / 2)),
+ # AVX
+ '/vex' : lambda v: UdOpcodeTable.vex2idx(v),
+ '/vexw' : lambda v: 0 if v == '0' else 1,
+ '/vexl' : lambda v: 0 if v == '0' else 1,
+ # Vendor
+ '/vendor': lambda v: UdOpcodeTable.vendor2idx(v)
</ins><span class="cx"> }
</span><span class="cx">
</span><del>- InsnTable = []
- MnemonicsTable = []
</del><span class="cx">
</span><del>- ThreeDNowTable = {}
</del><ins>+ _TableInfo = {
+ 'opctbl' : { 'label' : 'UD_TAB__OPC_TABLE', 'size' : 256 },
+ '/sse' : { 'label' : 'UD_TAB__OPC_SSE', 'size' : 4 },
+ '/reg' : { 'label' : 'UD_TAB__OPC_REG', 'size' : 8 },
+ '/rm' : { 'label' : 'UD_TAB__OPC_RM', 'size' : 8 },
+ '/mod' : { 'label' : 'UD_TAB__OPC_MOD', 'size' : 2 },
+ '/m' : { 'label' : 'UD_TAB__OPC_MODE', 'size' : 2 },
+ '/x87' : { 'label' : 'UD_TAB__OPC_X87', 'size' : 64 },
+ '/a' : { 'label' : 'UD_TAB__OPC_ASIZE', 'size' : 3 },
+ '/o' : { 'label' : 'UD_TAB__OPC_OSIZE', 'size' : 3 },
+ '/3dnow' : { 'label' : 'UD_TAB__OPC_3DNOW', 'size' : 256 },
+ '/vendor' : { 'label' : 'UD_TAB__OPC_VENDOR', 'size' : 3 },
+ '/vex' : { 'label' : 'UD_TAB__OPC_VEX', 'size' : 16 },
+ '/vexw' : { 'label' : 'UD_TAB__OPC_VEX_W', 'size' : 2 },
+ '/vexl' : { 'label' : 'UD_TAB__OPC_VEX_L', 'size' : 2 },
+ }
</ins><span class="cx">
</span><del>- def sizeOfTable( self, t ):
- return self.TableInfo[ t ][ 'size' ]
</del><span class="cx">
</span><del>- def nameOfTable( self, t ):
- return self.TableInfo[ t ][ 'name' ]
</del><ins>+ def __init__(self, typ):
+ assert typ in self._TableInfo
+ self._typ = typ
+ self._entries = {}
</ins><span class="cx">
</span><del>- #
- # Updates a table entry: If the entry doesn't exist
- # it will create the entry, otherwise, it will walk
- # while validating the path.
- #
- def updateTable( self, table, index, type, meta ):
- if not index in table[ 'entries' ]:
- table[ 'entries' ][ index ] = { 'type' : type, 'entries' : {}, 'meta' : meta }
- if table[ 'entries' ][ index ][ 'type' ] != type:
- raise NameError( "error: violation in opcode mapping (overwrite) %s with %s." %
- ( table[ 'entries' ][ index ][ 'type' ], type) )
- return table[ 'entries' ][ index ]
</del><span class="cx">
</span><del>- class Insn:
- """An abstract type representing an instruction in the opcode map.
</del><ins>+ def size(self):
+ return self._TableInfo[self._typ]['size']
+
+ def entries(self):
+ return itemslist(self._entries)
+
+ def numEntries(self):
+ return len(self._entries.keys())
+
+ def label(self):
+ return self._TableInfo[self._typ]['label']
+
+ def typ(self):
+ return self._typ
+
+ def meta(self):
+ return self._typ
+
+
+ def __str__(self):
+ return "table-%s" % self._typ
+
+
+ def add(self, opc, obj):
+ typ = UdOpcodeTable.getOpcodeTyp(opc)
+ idx = UdOpcodeTable.getOpcodeIdx(opc)
+ if self._typ != typ or idx in self._entries:
+ raise CollisionError()
+ self._entries[idx] = obj
+
+
+ def lookup(self, opc):
+ typ = UdOpcodeTable.getOpcodeTyp(opc)
+ idx = UdOpcodeTable.getOpcodeIdx(opc)
+ if self._typ != typ:
+ raise UdOpcodeTable.CollisionError("%s <-> %s" % (self._typ, typ))
+ return self._entries.get(idx, None)
+
+
+ def entryAt(self, index):
+ """Returns the entry at a given index of the table,
+ None if there is none. Raises an exception if the
+ index is out of bounds.
</ins><span class="cx"> """
</span><ins>+ if index < self.size():
+ return self._entries.get(index, None)
+ raise self.IndexError("index out of bounds: %s" % index)
</ins><span class="cx">
</span><del>- # A mapping of opcode extensions to their representational
- # values used in the opcode map.
- OpcExtMap = {
- '/rm' : lambda v: "%02x" % int(v, 16),
- '/x87' : lambda v: "%02x" % int(v, 16),
- '/3dnow' : lambda v: "%02x" % int(v, 16),
- '/reg' : lambda v: "%02x" % int(v, 16),
- # modrm.mod
- # (!11, 11) => (00, 01)
- '/mod' : lambda v: '00' if v == '!11' else '01',
- # Mode extensions:
- # (16, 32, 64) => (00, 01, 02)
- '/o' : lambda v: "%02x" % (int(v) / 32),
- '/a' : lambda v: "%02x" % (int(v) / 32),
- '/m' : lambda v: "%02x" % (int(v) / 32),
- '/sse' : lambda v: UdOpcodeTables.OpcExtIndex['sse'][v]
- }
</del><ins>+ def setEntryAt(self, index, obj):
+ if index < self.size():
+ self._entries[index] = obj
+ else:
+ raise self.IndexError("index out of bounds: %s" % index)
</ins><span class="cx">
</span><del>- def __init__(self, prefixes, mnemonic, opcodes, operands, vendor):
- self.opcodes = opcodes
- self.prefixes = prefixes
- self.mnemonic = mnemonic
- self.operands = operands
- self.vendor = vendor
- self.opcext = {}
</del><ins>+ @classmethod
+ def getOpcodeTyp(cls, opc):
+ if opc.startswith('/'):
+ return opc.split('=')[0]
+ else:
+ return 'opctbl'
</ins><span class="cx">
</span><del>- ssePrefix = None
- if self.opcodes[0] in ('ssef2', 'ssef3', 'sse66'):
- ssePrefix = self.opcodes[0][3:]
- self.opcodes.pop(0)
</del><span class="cx">
</span><del>- # do some preliminary decoding of the instruction type
- # 1byte, 2byte or 3byte instruction?
- self.nByteInsn = 1
- if self.opcodes[0] == '0f': # 2byte
- # 2+ byte opcodes are always disambiguated by an
- # sse prefix, unless it is a 3d now instruction
- # which is 0f 0f ...
- if self.opcodes[1] != '0f' and ssePrefix is None:
- ssePrefix = 'none'
- if self.opcodes[1] in ('38', '3a'): # 3byte
- self.nByteInsn = 3
</del><ins>+ @classmethod
+ def getOpcodeIdx(cls, opc):
+ if opc.startswith('/'):
+ typ, v = opc.split('=')
+ return cls.OpcExtMap[typ](v)
+ else:
+ # plain opctbl opcode
+ return int(opc, 16)
+
+
+ @classmethod
+ def getLabels(cls):
+ """Returns a list of all labels"""
+ return [cls._TableInfo[k]['label'] for k in cls._TableInfo.keys()]
+
+
+class UdOpcodeTables(object):
+ """Collection of opcode tables
+ """
+
+ class CollisionError(Exception):
+ def __init__(self, obj1, obj2):
+ self.obj1, self.obj2 = obj1, obj2
+
+ def newTable(self, typ):
+ """Create a new opcode table of a give type `typ`. """
+ tbl = UdOpcodeTable(typ)
+ self._tables.append(tbl)
+ return tbl
+
+ def mkTrie(self, opcodes, obj):
+ """Recursively contruct a trie entry mapping a string of
+ opcodes to an object.
+ """
+ if len(opcodes) == 0:
+ return obj
+ opc = opcodes[0]
+ tbl = self.newTable(UdOpcodeTable.getOpcodeTyp(opc))
+ tbl.add(opc, self.mkTrie(opcodes[1:], obj))
+ return tbl
+
+ def walk(self, tbl, opcodes):
+ """Walk down the opcode trie, starting at a given opcode
+ table, given a string of opcodes. Return None if unable
+ to walk, the object at the leaf otherwise.
+ """
+ opc = opcodes[0]
+ e = tbl.lookup(opc)
+ if e is None:
+ return None
+ elif isinstance(e, UdOpcodeTable) and len(opcodes[1:]):
+ return self.walk(e, opcodes[1:])
+ return e
+
+ def map(self, tbl, opcodes, obj):
+ """Create a mapping from a given string of opcodes to an
+ object in the opcode trie. Constructs trie branches as
+ needed.
+ """
+ opc = opcodes[0]
+ e = tbl.lookup(opc)
+ if e is None:
+ tbl.add(opc, self.mkTrie(opcodes[1:], obj))
+ else:
+ if len(opcodes[1:]) == 0:
+ raise self.CollisionError(e, obj)
+ self.map(e, opcodes[1:], obj)
+
+ def __init__(self, xml):
+ self._tables = []
+ self._insns = []
+ self._mnemonics = {}
+
+ # The root table is always a 256 entry opctbl, indexed
+ # by a plain opcode byte
+ self.root = self.newTable('opctbl')
+
+ if os.getenv("UD_OPCODE_DEBUG"):
+ self._logFh = open("opcodeTables.log", "w")
+
+ # add an invalid instruction entry without any mapping
+ # in the opcode tables.
+ self.invalidInsn = UdInsnDef(mnemonic="invalid", opcodes=[], cpuid=[],
+ operands=[], prefixes=[])
+ self._insns.append(self.invalidInsn)
+
+ # Construct UdOpcodeTables object from the given
+ # udis86 optable.xml
+ for insn in self.__class__.parseOptableXML(xml):
+ self.addInsnDef(insn)
+ self.patchAvx2byte()
+ self.mergeSSENONE()
+ self.printStats()
+
+ def log(self, s):
+ if os.getenv("UD_OPCODE_DEBUG"):
+ self._logFh.write(s + "\n")
+
+
+ def mergeSSENONE(self):
+ """Merge sse tables with only one entry for /sse=none
+ """
+ for table in self._tables:
+ for k, e in table.entries():
+ if isinstance(e, UdOpcodeTable) and e.typ() == '/sse':
+ if e.numEntries() == 1:
+ sse = e.lookup("/sse=none")
+ if sse:
+ table.setEntryAt(k, sse)
+ uniqTables = {}
+ def genTableList(tbl):
+ if tbl not in uniqTables:
+ self._tables.append(tbl)
+ uniqTables[tbl] = 1
+ for k, e in tbl.entries():
+ if isinstance(e, UdOpcodeTable):
+ genTableList(e)
+ self._tables = []
+ genTableList(self.root)
+
+
+ def patchAvx2byte(self):
+ # create avx tables
+ for pp in (None, 'f2', 'f3', '66'):
+ for m in (None, '0f', '0f38', '0f3a'):
+ if pp is None and m is None:
+ continue
+ if pp is None:
+ vex = m
+ elif m is None:
+ vex = pp
</ins><span class="cx"> else:
</span><del>- self.nByteInsn = 2
-
- # The opcode that indexes into the opcode table.
- self.opcode = self.opcodes[self.nByteInsn - 1]
-
- # Record opcode extensions
- for opcode in self.opcodes[self.nByteInsn:]:
- arg, val = opcode.split('=')
- self.opcext[arg] = self.OpcExtMap[arg](val)
</del><ins>+ vex = pp + '_' + m
+ table = self.walk(self.root, ('c4', '/vex=' + vex))
+ self.map(self.root, ('c5', '/vex=' + vex), table)
</ins><span class="cx">
</span><del>- # Record sse extension: the reason sse extension is handled
- # separately is that historically sse was handled as a first
- # class opcode, not as an extension. Now that sse is handled
- # as an extension, we do the manual conversion here, as opposed
- # to modifying the opcode xml file.
- if ssePrefix is not None:
- self.opcext['/sse'] = self.OpcExtMap['/sse'](ssePrefix)
</del><span class="cx">
</span><del>- def parse(self, table, insn):
- index = insn.opcodes[0];
- if insn.nByteInsn > 1:
- assert index == '0f'
- table = self.updateTable(table, index, 'opctbl', '0f')
- index = insn.opcodes[1]
</del><ins>+ def addInsn(self, **insnDef):
</ins><span class="cx">
</span><del>- if insn.nByteInsn == 3:
- table = self.updateTable(table, index, 'opctbl', index)
- index = insn.opcodes[2]
</del><ins>+ # Canonicalize opcode list
+ opcexts = insnDef['opcexts']
+ opcodes = list(insnDef['opcodes'])
</ins><span class="cx">
</span><del>- # Walk down the tree, create levels as needed, for opcode
- # extensions. The order is important, and determines how
</del><ins>+ # Re-order vex
+ if '/vex' in opcexts:
+ assert opcodes[0] == 'c4' or opcodes[0] == 'c5'
+ opcodes.insert(1, '/vex=' + opcexts['/vex'])
+
+ # Add extensions. The order is important, and determines how
</ins><span class="cx"> # well the opcode table is packed. Also note, /sse must be
</span><span class="cx"> # before /o, because /sse may consume operand size prefix
</span><span class="cx"> # affect the outcome of /o.
</span><del>- for ext in ('/mod', '/x87', '/reg', '/rm', '/sse',
- '/o', '/a', '/m', '/3dnow'):
- if ext in insn.opcext:
- table = self.updateTable(table, index, ext, ext)
- index = insn.opcext[ext]
</del><ins>+ for ext in ('/mod', '/x87', '/reg', '/rm', '/sse', '/o', '/a', '/m',
+ '/vexw', '/vexl', '/3dnow', '/vendor'):
+ if ext in opcexts:
+ opcodes.append(ext + '=' + opcexts[ext])
</ins><span class="cx">
</span><del>- # additional table for disambiguating vendor
- if len(insn.vendor):
- table = self.updateTable(table, index, 'vendor', insn.vendor)
- index = self.OpcExtIndex['vendor'][insn.vendor]
</del><ins>+ insn = UdInsnDef(mnemonic = insnDef['mnemonic'],
+ prefixes = insnDef['prefixes'],
+ operands = insnDef['operands'],
+ opcodes = opcodes,
+ cpuid = insnDef['cpuid'])
+ try:
+ self.map(self.root, opcodes, insn)
+ except self.CollisionError as e:
+ self.pprint()
+ print(opcodes, insn, str(e.obj1), str(e.obj2))
+ raise
+ except Exception as e:
+ self.pprint()
+ raise
+ self._insns.append(insn)
+ # add to lookup by mnemonic structure
+ if insn.mnemonic not in self._mnemonics:
+ self._mnemonics[insn.mnemonic] = [ insn ]
+ else:
+ self._mnemonics[insn.mnemonic].append(insn)
</ins><span class="cx">
</span><del>- # make leaf node entries
- leaf = self.updateTable(table, index, 'insn', '')
</del><span class="cx">
</span><del>- leaf['mnemonic'] = insn.mnemonic
- leaf['prefixes'] = insn.prefixes
- leaf['operands'] = insn.operands
</del><ins>+ def addInsnDef(self, insnDef):
+ opcodes = []
+ opcexts = {}
</ins><span class="cx">
</span><del>- # add instruction to linear table of instruction forms
- self.InsnTable.append({ 'prefixes' : insn.prefixes,
- 'mnemonic' : insn.mnemonic,
- 'operands' : insn.operands })
</del><ins>+ # pack plain opcodes first, and collect opcode
+ # extensions
+ for opc in insnDef['opcodes']:
+ if not opc.startswith('/'):
+ opcodes.append(opc)
+ else:
+ e, v = opc.split('=')
+ opcexts[e] = v
</ins><span class="cx">
</span><del>- # add mnemonic to mnemonic table
- if not insn.mnemonic in self.MnemonicsTable:
- self.MnemonicsTable.append(insn.mnemonic)
</del><ins>+ # treat vendor as an opcode extension
+ if len(insnDef['vendor']):
+ opcexts['/vendor'] = insnDef['vendor'][0]
</ins><span class="cx">
</span><ins>+ if insnDef['mnemonic'] in ('lds', 'les'):
+ #
+ # Massage lds and les, which share the same prefix as AVX
+ # instructions, to work well with the opcode tree.
+ #
+ opcexts['/vex'] = 'none'
+ elif '/vex' in opcexts:
+ # A proper avx instruction definition; make sure there are
+ # no legacy opcode extensions
+ assert '/sse' not in opcodes
</ins><span class="cx">
</span><del>- # Adds an instruction definition to the opcode tables
- def addInsnDef( self, prefixes, mnemonic, opcodes, operands, vendor ):
- insn = self.Insn(prefixes=prefixes,
- mnemonic=mnemonic,
- opcodes=opcodes,
- operands=operands,
- vendor=vendor)
- self.parse(self.OpcodeTable0, insn)
</del><ins>+ # make sure the opcode definitions don't already include
+ # the avx prefixes.
+ assert opcodes[0] not in ('c4', 'c5')
</ins><span class="cx">
</span><del>- def print_table( self, table, pfxs ):
- print("%s |" % pfxs)
- keys = table[ 'entries' ].keys()
- if ( len( keys ) ):
- keys.sort()
- for idx in keys:
- e = table[ 'entries' ][ idx ]
- if e[ 'type' ] == 'insn':
- print("%s |-<%s>" % ( pfxs, idx )),
- print("%s %s" % ( e[ 'mnemonic' ], ' '.join( e[ 'operands'] )))
- else:
- print("%s |-<%s> %s" % ( pfxs, idx, e['type'] ))
- self.print_table( e, pfxs + ' |' )
</del><ins>+ # An avx only instruction is defined by the /vex= opcode
+ # extension. They do not include the c4 (long form) or
+ # c5 (short form) prefix. As part of opcode table generate,
+ # here we create the long form definition, and then patch
+ # the table for c5 in a later stage.
+ # Construct a long-form definition of the avx instruction
+ opcodes.insert(0, 'c4')
+ elif (opcodes[0] == '0f' and opcodes[1] != '0f' and
+ '/sse' not in opcexts):
+ # Make all 2-byte opcode form isntructions play nice with sse
+ # opcode maps.
+ opcexts['/sse'] = 'none'
</ins><span class="cx">
</span><del>- def print_tree( self ):
- self.print_table( self.OpcodeTable0, '' )
</del><ins>+ # legacy sse defs that get promoted to avx
+ fn = self.addInsn
+ if 'avx' in insnDef['cpuid'] and '/sse' in opcexts:
+ fn = self.addSSE2AVXInsn
+
+ fn(mnemonic = insnDef['mnemonic'],
+ prefixes = insnDef['prefixes'],
+ opcodes = opcodes,
+ opcexts = opcexts,
+ operands = insnDef['operands'],
+ cpuid = insnDef['cpuid'])
+
+
+ def addSSE2AVXInsn(self, **insnDef):
+ """Add an instruction definition containing an avx cpuid bit, but
+ declared in its legacy SSE form. The function splits the
+ definition to create two new definitions, one for SSE and one
+ promoted to an AVX form.
+ """
+
+ # SSE
+ ssemnemonic = insnDef['mnemonic']
+ sseopcodes = insnDef['opcodes']
+ # remove vex opcode extensions
+ sseopcexts = dict([(e, v) for e, v in itemslist(insnDef['opcexts'])
+ if not e.startswith('/vex')])
+ # strip out avx operands, preserving relative ordering
+ # of remaining operands
+ sseoperands = [opr for opr in insnDef['operands']
+ if opr not in ('H', 'L')]
+ # strip out avx prefixes
+ sseprefixes = [pfx for pfx in insnDef['prefixes']
+ if not pfx.startswith('vex')]
+ # strip out avx bits from cpuid
+ ssecpuid = [flag for flag in insnDef['cpuid']
+ if not flag.startswith('avx')]
+
+ self.addInsn(mnemonic = ssemnemonic,
+ prefixes = sseprefixes,
+ opcodes = sseopcodes,
+ opcexts = sseopcexts,
+ operands = sseoperands,
+ cpuid = ssecpuid)
+
+ # AVX
+ vexmnemonic = 'v' + insnDef['mnemonic']
+ vexprefixes = insnDef['prefixes']
+ vexopcodes = ['c4']
+ vexopcexts = dict([(e, insnDef['opcexts'][e])
+ for e in insnDef['opcexts'] if e != '/sse'])
+ vexopcexts['/vex'] = insnDef['opcexts']['/sse'] + '_' + '0f'
+ if insnDef['opcodes'][1] == '38' or insnDef['opcodes'][1] == '3a':
+ vexopcexts['/vex'] += insnDef['opcodes'][1]
+ vexopcodes.extend(insnDef['opcodes'][2:])
+ else:
+ vexopcodes.extend(insnDef['opcodes'][1:])
+ vexoperands = []
+ for o in insnDef['operands']:
+ # make the operand size explicit: x
+ if o in ('V', 'W', 'H', 'U'):
+ o = o + 'x'
+ vexoperands.append(o)
+ vexcpuid = [flag for flag in insnDef['cpuid']
+ if not flag.startswith('sse')]
+
+ self.addInsn(mnemonic = vexmnemonic,
+ prefixes = vexprefixes,
+ opcodes = vexopcodes,
+ opcexts = vexopcexts,
+ operands = vexoperands,
+ cpuid = vexcpuid)
+
+ def getInsnList(self):
+ """Returns a list of all instructions in the collection"""
+ return self._insns
+
+
+ def getTableList(self):
+ """Returns a list of all tables in the collection"""
+ return self._tables
+
+ def getMnemonicsList(self):
+ """Returns a sorted list of mnemonics"""
+ return sorted(self._mnemonics.keys())
+
+
+ def pprint(self):
+ def printWalk(tbl, indent=""):
+ entries = tbl.entries()
+ for k, e in entries:
+ if isinstance(e, UdOpcodeTable):
+ self.log("%s |-<%02x> %s" % (indent, k, e))
+ printWalk(e, indent + " |")
+ elif isinstance(e, UdInsnDef):
+ self.log("%s |-<%02x> %s" % (indent, k, e))
+ printWalk(self.root)
+
+
+ def printStats(self):
+ tables = self.getTableList()
+ self.log("stats: ")
+ self.log(" Num tables = %d" % len(tables))
+ self.log(" Num insnDefs = %d" % len(self.getInsnList()))
+ self.log(" Num insns = %d" % len(self.getMnemonicsList()))
+
+ totalSize = 0
+ totalEntries = 0
+ for table in tables:
+ totalSize += table.size()
+ totalEntries += table.numEntries()
+ self.log(" Packing Ratio = %d%%" % ((totalEntries * 100) / totalSize))
+ self.log("--------------------")
+
+ self.pprint()
+
+
+ @staticmethod
+ def parseOptableXML(xml):
+ """Parse udis86 optable.xml file and return list of
+ instruction definitions.
+ """
+ from xml.dom import minidom
+
+ xmlDoc = minidom.parse(xml)
+ tlNode = xmlDoc.firstChild
+ insns = []
+
+ while tlNode and tlNode.localName != "x86optable":
+ tlNode = tlNode.nextSibling
+
+ for insnNode in tlNode.childNodes:
+ if not insnNode.localName:
+ continue
+ if insnNode.localName != "instruction":
+ raise Exception("warning: invalid insn node - %s" % insnNode.localName)
+ mnemonic = insnNode.getElementsByTagName('mnemonic')[0].firstChild.data
+ vendor, cpuid = '', []
+
+ for node in insnNode.childNodes:
+ if node.localName == 'vendor':
+ vendor = node.firstChild.data.split()
+ elif node.localName == 'cpuid':
+ cpuid = node.firstChild.data.split()
+
+ for node in insnNode.childNodes:
+ if node.localName == 'def':
+ insnDef = { 'pfx' : [] }
+ for node in node.childNodes:
+ if not node.localName:
+ continue
+ if node.localName in ('pfx', 'opc', 'opr', 'vendor', 'cpuid'):
+ insnDef[node.localName] = node.firstChild.data.split()
+ elif node.localName == 'mode':
+ insnDef['pfx'].extend(node.firstChild.data.split())
+ insns.append({'prefixes' : insnDef.get('pfx', []),
+ 'mnemonic' : mnemonic,
+ 'opcodes' : insnDef.get('opc', []),
+ 'operands' : insnDef.get('opr', []),
+ 'vendor' : insnDef.get('vendor', vendor),
+ 'cpuid' : insnDef.get('cpuid', cpuid)})
+ return insns
</ins></span></pre></div>
<a id="trunkSourceJavaScriptCoredisassemblerudis86ud_optablepy"></a>
<div class="delfile"><h4>Deleted: trunk/Source/JavaScriptCore/disassembler/udis86/ud_optable.py (198831 => 198832)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/disassembler/udis86/ud_optable.py 2016-03-30 07:14:10 UTC (rev 198831)
+++ trunk/Source/JavaScriptCore/disassembler/udis86/ud_optable.py 2016-03-30 07:17:14 UTC (rev 198832)
</span><span class="lines">@@ -1,103 +0,0 @@
</span><del>-# udis86 - scripts/ud_optable.py (optable.xml parser)
-#
-# Copyright (c) 2009 Vivek Thampi
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without modification,
-# are permitted provided that the following conditions are met:
-#
-# * Redistributions of source code must retain the above copyright notice,
-# this list of conditions and the following disclaimer.
-# * Redistributions in binary form must reproduce the above copyright notice,
-# this list of conditions and the following disclaimer in the documentation
-# and/or other materials provided with the distribution.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-import os
-import sys
-from xml.dom import minidom
-
-class UdOptableXmlParser:
-
- def parseDef( self, node ):
- ven = ''
- pfx = []
- opc = []
- opr = []
- for def_node in node.childNodes:
- if not def_node.localName:
- continue
- if def_node.localName == 'pfx':
- pfx = def_node.firstChild.data.split();
- elif def_node.localName == 'opc':
- opc = def_node.firstChild.data.split();
- elif def_node.localName == 'opr':
- opr = def_node.firstChild.data.split();
- elif def_node.localName == 'mode':
- pfx.extend( def_node.firstChild.data.split() );
- elif def_node.localName == 'syn':
- pfx.extend( def_node.firstChild.data.split() );
- elif def_node.localName == 'vendor':
- ven = ( def_node.firstChild.data );
- else:
- print("warning: invalid node - %s" % def_node.localName)
- continue
- return ( pfx, opc, opr, ven )
-
- def parse( self, xml, fn ):
- xmlDoc = minidom.parse( xml )
- self.TlNode = xmlDoc.firstChild
-
- while self.TlNode and self.TlNode.localName != "x86optable":
- self.TlNode = self.TlNode.nextSibling
-
- for insnNode in self.TlNode.childNodes:
- if not insnNode.localName:
- continue
- if insnNode.localName != "instruction":
- print("warning: invalid insn node - %s" % insnNode.localName)
- continue
-
- mnemonic = insnNode.getElementsByTagName( 'mnemonic' )[ 0 ].firstChild.data
- vendor = ''
-
- for node in insnNode.childNodes:
- if node.localName == 'vendor':
- vendor = node.firstChild.data
- elif node.localName == 'def':
- ( prefixes, opcodes, operands, local_vendor ) = \
- self.parseDef( node )
- if ( len( local_vendor ) ):
- vendor = local_vendor
- # callback
- fn( prefixes, mnemonic, opcodes, operands, vendor )
-
-
-def printFn( pfx, mnm, opc, opr, ven ):
- print('def: '),
- if len( pfx ):
- print(' '.join( pfx )),
- print("%s %s %s %s" % \
- ( mnm, ' '.join( opc ), ' '.join( opr ), ven ))
-
-
-def parse( xml, callback ):
- parser = UdOptableXmlParser()
- parser.parse( xml, callback )
-
-def main():
- parser = UdOptableXmlParser()
- parser.parse( sys.argv[ 1 ], printFn )
-
-if __name__ == "__main__":
- main()
</del></span></pre></div>
<a id="trunkSourceJavaScriptCoredisassemblerudis86udis86c"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/disassembler/udis86/udis86.c (198831 => 198832)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/disassembler/udis86/udis86.c 2016-03-30 07:14:10 UTC (rev 198831)
+++ trunk/Source/JavaScriptCore/disassembler/udis86/udis86.c 2016-03-30 07:17:14 UTC (rev 198832)
</span><span class="lines">@@ -1,6 +1,6 @@
</span><span class="cx"> /* udis86 - libudis86/udis86.c
</span><span class="cx"> *
</span><del>- * Copyright (c) 2002-2009 Vivek Thampi
</del><ins>+ * Copyright (c) 2002-2013 Vivek Thampi
</ins><span class="cx"> * All rights reserved.
</span><span class="cx"> *
</span><span class="cx"> * Redistribution and use in source and binary forms, with or without modification,
</span><span class="lines">@@ -28,16 +28,19 @@
</span><span class="cx">
</span><span class="cx"> #if USE(UDIS86)
</span><span class="cx">
</span><del>-#include "udis86_input.h"
</del><ins>+#include "udis86_udint.h"
</ins><span class="cx"> #include "udis86_extern.h"
</span><ins>+#include "udis86_decode.h"
</ins><span class="cx">
</span><del>-#ifndef __UD_STANDALONE__
-# include <stdlib.h>
-# include <string.h>
-#endif /* __UD_STANDALONE__ */
</del><ins>+#if !defined(__UD_STANDALONE__)
+#include <string.h>
+#endif /* !__UD_STANDALONE__ */
</ins><span class="cx">
</span><ins>+static void ud_inp_init(struct ud *u);
+
</ins><span class="cx"> /* =============================================================================
</span><del>- * ud_init() - Initializes ud_t object.
</del><ins>+ * ud_init
+ * Initializes ud_t object.
</ins><span class="cx"> * =============================================================================
</span><span class="cx"> */
</span><span class="cx"> extern void
</span><span class="lines">@@ -50,30 +53,34 @@
</span><span class="cx"> #ifndef __UD_STANDALONE__
</span><span class="cx"> ud_set_input_file(u, stdin);
</span><span class="cx"> #endif /* __UD_STANDALONE__ */
</span><ins>+
+ ud_set_asm_buffer(u, u->asm_buf_int, sizeof(u->asm_buf_int));
</ins><span class="cx"> }
</span><span class="cx">
</span><ins>+
</ins><span class="cx"> /* =============================================================================
</span><del>- * ud_disassemble() - disassembles one instruction and returns the number of
- * bytes disassembled. A zero means end of disassembly.
</del><ins>+ * ud_disassemble
+ * Disassembles one instruction and returns the number of
+ * bytes disassembled. A zero means end of disassembly.
</ins><span class="cx"> * =============================================================================
</span><span class="cx"> */
</span><span class="cx"> extern unsigned int
</span><span class="cx"> ud_disassemble(struct ud* u)
</span><span class="cx"> {
</span><del>- if (ud_input_end(u))
- return 0;
</del><ins>+ int len;
+ if (u->inp_end) {
+ return 0;
+ }
+ if ((len = ud_decode(u)) > 0) {
+ if (u->translator != NULL) {
+ u->asm_buf[0] = '\0';
+ u->translator(u);
+ }
+ }
+ return len;
+}
</ins><span class="cx">
</span><del>-
- u->insn_buffer[0] = u->insn_hexcode[0] = 0;
</del><span class="cx">
</span><del>-
- if (ud_decode(u) == 0)
- return 0;
- if (u->translator)
- u->translator(u);
- return ud_insn_len(u);
-}
-
</del><span class="cx"> /* =============================================================================
</span><span class="cx"> * ud_set_mode() - Set Disassemly Mode.
</span><span class="cx"> * =============================================================================
</span><span class="lines">@@ -82,10 +89,10 @@
</span><span class="cx"> ud_set_mode(struct ud* u, uint8_t m)
</span><span class="cx"> {
</span><span class="cx"> switch(m) {
</span><del>- case 16:
- case 32:
- case 64: u->dis_mode = m ; return;
- default: u->dis_mode = 16; return;
</del><ins>+ case 16:
+ case 32:
+ case 64: u->dis_mode = m ; return;
+ default: u->dis_mode = 16; return;
</ins><span class="cx"> }
</span><span class="cx"> }
</span><span class="cx">
</span><span class="lines">@@ -97,14 +104,14 @@
</span><span class="cx"> ud_set_vendor(struct ud* u, unsigned v)
</span><span class="cx"> {
</span><span class="cx"> switch(v) {
</span><del>- case UD_VENDOR_INTEL:
- u->vendor = v;
- break;
- case UD_VENDOR_ANY:
- u->vendor = v;
- break;
- default:
- u->vendor = UD_VENDOR_AMD;
</del><ins>+ case UD_VENDOR_INTEL:
+ u->vendor = v;
+ break;
+ case UD_VENDOR_ANY:
+ u->vendor = v;
+ break;
+ default:
+ u->vendor = UD_VENDOR_AMD;
</ins><span class="cx"> }
</span><span class="cx"> }
</span><span class="cx">
</span><span class="lines">@@ -132,18 +139,18 @@
</span><span class="cx"> * ud_insn() - returns the disassembled instruction
</span><span class="cx"> * =============================================================================
</span><span class="cx"> */
</span><del>-extern char*
-ud_insn_asm(struct ud* u)
</del><ins>+const char*
+ud_insn_asm(const struct ud* u)
</ins><span class="cx"> {
</span><del>- return u->insn_buffer;
</del><ins>+ return u->asm_buf;
</ins><span class="cx"> }
</span><span class="cx">
</span><span class="cx"> /* =============================================================================
</span><span class="cx"> * ud_insn_offset() - Returns the offset.
</span><span class="cx"> * =============================================================================
</span><span class="cx"> */
</span><del>-extern uint64_t
-ud_insn_off(struct ud* u)
</del><ins>+uint64_t
+ud_insn_off(const struct ud* u)
</ins><span class="cx"> {
</span><span class="cx"> return u->insn_offset;
</span><span class="cx"> }
</span><span class="lines">@@ -153,30 +160,303 @@
</span><span class="cx"> * ud_insn_hex() - Returns hex form of disassembled instruction.
</span><span class="cx"> * =============================================================================
</span><span class="cx"> */
</span><del>-extern char*
</del><ins>+const char*
</ins><span class="cx"> ud_insn_hex(struct ud* u)
</span><span class="cx"> {
</span><ins>+ u->insn_hexcode[0] = 0;
+ if (!u->error) {
+ unsigned int i;
+ const unsigned char *src_ptr = ud_insn_ptr(u);
+ char* src_hex;
+ src_hex = (char*) u->insn_hexcode;
+ /* for each byte used to decode instruction */
+ for (i = 0; i < ud_insn_len(u) && i < sizeof(u->insn_hexcode) / 2;
+ ++i, ++src_ptr) {
+ sprintf(src_hex, "%02x", *src_ptr & 0xFF);
+ src_hex += 2;
+ }
+ }
</ins><span class="cx"> return u->insn_hexcode;
</span><span class="cx"> }
</span><span class="cx">
</span><ins>+
</ins><span class="cx"> /* =============================================================================
</span><del>- * ud_insn_ptr() - Returns code disassembled.
</del><ins>+ * ud_insn_ptr
+ * Returns a pointer to buffer containing the bytes that were
+ * disassembled.
</ins><span class="cx"> * =============================================================================
</span><span class="cx"> */
</span><del>-extern uint8_t*
-ud_insn_ptr(struct ud* u)
</del><ins>+extern const uint8_t*
+ud_insn_ptr(const struct ud* u)
</ins><span class="cx"> {
</span><del>- return u->inp_sess;
</del><ins>+ return (u->inp_buf == NULL) ?
+ u->inp_sess : u->inp_buf + (u->inp_buf_index - u->inp_ctr);
</ins><span class="cx"> }
</span><span class="cx">
</span><ins>+
</ins><span class="cx"> /* =============================================================================
</span><del>- * ud_insn_len() - Returns the count of bytes disassembled.
</del><ins>+ * ud_insn_len
+ * Returns the count of bytes disassembled.
</ins><span class="cx"> * =============================================================================
</span><span class="cx"> */
</span><span class="cx"> extern unsigned int
</span><del>-ud_insn_len(struct ud* u)
</del><ins>+ud_insn_len(const struct ud* u)
</ins><span class="cx"> {
</span><span class="cx"> return u->inp_ctr;
</span><span class="cx"> }
</span><span class="cx">
</span><ins>+
+/* =============================================================================
+ * ud_insn_get_opr
+ * Return the operand struct representing the nth operand of
+ * the currently disassembled instruction. Returns NULL if
+ * there's no such operand.
+ * =============================================================================
+ */
+const struct ud_operand*
+ud_insn_opr(const struct ud *u, unsigned int n)
+{
+ if (n > 3 || u->operand[n].type == UD_NONE) {
+ return NULL;
+ } else {
+ return &u->operand[n];
+ }
+}
+
+
+/* =============================================================================
+ * ud_opr_is_sreg
+ * Returns non-zero if the given operand is of a segment register type.
+ * =============================================================================
+ */
+int
+ud_opr_is_sreg(const struct ud_operand *opr)
+{
+ return opr->type == UD_OP_REG &&
+ opr->base >= UD_R_ES &&
+ opr->base <= UD_R_GS;
+}
+
+
+/* =============================================================================
+ * ud_opr_is_sreg
+ * Returns non-zero if the given operand is of a general purpose
+ * register type.
+ * =============================================================================
+ */
+int
+ud_opr_is_gpr(const struct ud_operand *opr)
+{
+ return opr->type == UD_OP_REG &&
+ opr->base >= UD_R_AL &&
+ opr->base <= UD_R_R15;
+}
+
+
+/* =============================================================================
+ * ud_set_user_opaque_data
+ * ud_get_user_opaque_data
+ * Get/set user opaqute data pointer
+ * =============================================================================
+ */
+void
+ud_set_user_opaque_data(struct ud * u, void* opaque)
+{
+ u->user_opaque_data = opaque;
+}
+
+void*
+ud_get_user_opaque_data(const struct ud *u)
+{
+ return u->user_opaque_data;
+}
+
+
+/* =============================================================================
+ * ud_set_asm_buffer
+ * Allow the user to set an assembler output buffer. If `buf` is NULL,
+ * we switch back to the internal buffer.
+ * =============================================================================
+ */
+void
+ud_set_asm_buffer(struct ud *u, char *buf, size_t size)
+{
+ if (buf == NULL) {
+ ud_set_asm_buffer(u, u->asm_buf_int, sizeof(u->asm_buf_int));
+ } else {
+ u->asm_buf = buf;
+ u->asm_buf_size = size;
+ }
+}
+
+
+/* =============================================================================
+ * ud_set_sym_resolver
+ * Set symbol resolver for relative targets used in the translation
+ * phase.
+ *
+ * The resolver is a function that takes a uint64_t address and returns a
+ * symbolic name for the that address. The function also takes a second
+ * argument pointing to an integer that the client can optionally set to a
+ * non-zero value for offsetted targets. (symbol+offset) The function may
+ * also return NULL, in which case the translator only prints the target
+ * address.
+ *
+ * The function pointer maybe NULL which resets symbol resolution.
+ * =============================================================================
+ */
+void
+ud_set_sym_resolver(struct ud *u, const char* (*resolver)(struct ud*,
+ uint64_t addr,
+ int64_t *offset))
+{
+ u->sym_resolver = resolver;
+}
+
+
+/* =============================================================================
+ * ud_insn_mnemonic
+ * Return the current instruction mnemonic.
+ * =============================================================================
+ */
+enum ud_mnemonic_code
+ud_insn_mnemonic(const struct ud *u)
+{
+ return u->mnemonic;
+}
+
+
+/* =============================================================================
+ * ud_lookup_mnemonic
+ * Looks up mnemonic code in the mnemonic string table.
+ * Returns NULL if the mnemonic code is invalid.
+ * =============================================================================
+ */
+const char*
+ud_lookup_mnemonic(enum ud_mnemonic_code c)
+{
+ if (c < UD_MAX_MNEMONIC_CODE) {
+ return ud_mnemonics_str[c];
+ } else {
+ return NULL;
+ }
+}
+
+
+/*
+ * ud_inp_init
+ * Initializes the input system.
+ */
+static void
+ud_inp_init(struct ud *u)
+{
+ u->inp_hook = NULL;
+ u->inp_buf = NULL;
+ u->inp_buf_size = 0;
+ u->inp_buf_index = 0;
+ u->inp_curr = 0;
+ u->inp_ctr = 0;
+ u->inp_end = 0;
+ u->inp_peek = UD_EOI;
+ UD_NON_STANDALONE(u->inp_file = NULL);
+}
+
+
+/* =============================================================================
+ * ud_inp_set_hook
+ * Sets input hook.
+ * =============================================================================
+ */
+void
+ud_set_input_hook(register struct ud* u, int (*hook)(struct ud*))
+{
+ ud_inp_init(u);
+ u->inp_hook = hook;
+}
+
+/* =============================================================================
+ * ud_inp_set_buffer
+ * Set buffer as input.
+ * =============================================================================
+ */
+void
+ud_set_input_buffer(register struct ud* u, const uint8_t* buf, size_t len)
+{
+ ud_inp_init(u);
+ u->inp_buf = buf;
+ u->inp_buf_size = len;
+ u->inp_buf_index = 0;
+}
+
+
+#ifndef __UD_STANDALONE__
+/* =============================================================================
+ * ud_input_set_file
+ * Set FILE as input.
+ * =============================================================================
+ */
+static int
+inp_file_hook(struct ud* u)
+{
+ return fgetc(u->inp_file);
+}
+
+void
+ud_set_input_file(register struct ud* u, FILE* f)
+{
+ ud_inp_init(u);
+ u->inp_hook = inp_file_hook;
+ u->inp_file = f;
+}
+#endif /* __UD_STANDALONE__ */
+
+
+/* =============================================================================
+ * ud_input_skip
+ * Skip n input bytes.
+ * ============================================================================
+ */
+void
+ud_input_skip(struct ud* u, size_t n)
+{
+ if (u->inp_end) {
+ return;
+ }
+ if (u->inp_buf == NULL) {
+ while (n--) {
+ int c = u->inp_hook(u);
+ if (c == UD_EOI) {
+ goto eoi;
+ }
+ }
+ return;
+ } else {
+ if (n > u->inp_buf_size ||
+ u->inp_buf_index > u->inp_buf_size - n) {
+ u->inp_buf_index = u->inp_buf_size;
+ goto eoi;
+ }
+ u->inp_buf_index += n;
+ return;
+ }
+eoi:
+ u->inp_end = 1;
+ UDERR(u, "cannot skip, eoi received\b");
+ return;
+}
+
+
+/* =============================================================================
+ * ud_input_end
+ * Returns non-zero on end-of-input.
+ * =============================================================================
+ */
+int
+ud_input_end(const struct ud *u)
+{
+ return u->inp_end;
+}
+
</ins><span class="cx"> #endif // USE(UDIS86)
</span><ins>+
+/* vim:set ts=2 sw=2 expandtab */
</ins></span></pre></div>
<a id="trunkSourceJavaScriptCoredisassemblerudis86udis86_decodec"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/disassembler/udis86/udis86_decode.c (198831 => 198832)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/disassembler/udis86/udis86_decode.c 2016-03-30 07:14:10 UTC (rev 198831)
+++ trunk/Source/JavaScriptCore/disassembler/udis86/udis86_decode.c 2016-03-30 07:17:14 UTC (rev 198832)
</span><span class="lines">@@ -28,15 +28,11 @@
</span><span class="cx">
</span><span class="cx"> #if USE(UDIS86)
</span><span class="cx">
</span><ins>+#include "udis86_udint.h"
+#include "udis86_types.h"
</ins><span class="cx"> #include "udis86_extern.h"
</span><del>-#include "udis86_types.h"
-#include "udis86_input.h"
</del><span class="cx"> #include "udis86_decode.h"
</span><del>-#include <wtf/Assertions.h>
</del><span class="cx">
</span><del>-#define dbg(x, n...)
-/* #define dbg printf */
-
</del><span class="cx"> #ifndef __UD_STANDALONE__
</span><span class="cx"> # include <string.h>
</span><span class="cx"> #endif /* __UD_STANDALONE__ */
</span><span class="lines">@@ -44,15 +40,164 @@
</span><span class="cx"> /* The max number of prefixes to an instruction */
</span><span class="cx"> #define MAX_PREFIXES 15
</span><span class="cx">
</span><del>-/* instruction aliases and special cases */
-static struct ud_itab_entry s_ie__invalid =
- { UD_Iinvalid, O_NONE, O_NONE, O_NONE, P_none };
</del><ins>+/* rex prefix bits */
+#define REX_W(r) ( ( 0xF & ( r ) ) >> 3 )
+#define REX_R(r) ( ( 0x7 & ( r ) ) >> 2 )
+#define REX_X(r) ( ( 0x3 & ( r ) ) >> 1 )
+#define REX_B(r) ( ( 0x1 & ( r ) ) >> 0 )
+#define REX_PFX_MASK(n) ( ( P_REXW(n) << 3 ) | \
+ ( P_REXR(n) << 2 ) | \
+ ( P_REXX(n) << 1 ) | \
+ ( P_REXB(n) << 0 ) )
</ins><span class="cx">
</span><del>-static int
-decode_ext(struct ud *u, uint16_t ptr);
</del><ins>+/* scable-index-base bits */
+#define SIB_S(b) ( ( b ) >> 6 )
+#define SIB_I(b) ( ( ( b ) >> 3 ) & 7 )
+#define SIB_B(b) ( ( b ) & 7 )
</ins><span class="cx">
</span><ins>+/* modrm bits */
+#define MODRM_REG(b) ( ( ( b ) >> 3 ) & 7 )
+#define MODRM_NNN(b) ( ( ( b ) >> 3 ) & 7 )
+#define MODRM_MOD(b) ( ( ( b ) >> 6 ) & 3 )
+#define MODRM_RM(b) ( ( b ) & 7 )
</ins><span class="cx">
</span><del>-static inline int
</del><ins>+static int decode_ext(struct ud *u, uint16_t ptr);
+static int decode_opcode(struct ud *u);
+
+enum reg_class { /* register classes */
+ REGCLASS_GPR,
+ REGCLASS_MMX,
+ REGCLASS_CR,
+ REGCLASS_DB,
+ REGCLASS_SEG,
+ REGCLASS_XMM
+};
+
+ /*
+ * inp_start
+ * Should be called before each de-code operation.
+ */
+static void
+inp_start(struct ud *u)
+{
+ u->inp_ctr = 0;
+}
+
+static uint8_t
+inp_peek(struct ud *u)
+{
+ if (u->inp_end == 0) {
+ if (u->inp_buf != NULL) {
+ if (u->inp_buf_index < u->inp_buf_size) {
+ return u->inp_buf[u->inp_buf_index];
+ }
+ } else if (u->inp_peek != UD_EOI) {
+ return u->inp_peek;
+ } else {
+ int c;
+ if ((c = u->inp_hook(u)) != UD_EOI) {
+ u->inp_peek = c;
+ return u->inp_peek;
+ }
+ }
+ }
+ u->inp_end = 1;
+ UDERR(u, "byte expected, eoi received\n");
+ return 0;
+}
+
+static uint8_t
+inp_next(struct ud *u)
+{
+ if (u->inp_end == 0) {
+ if (u->inp_buf != NULL) {
+ if (u->inp_buf_index < u->inp_buf_size) {
+ u->inp_ctr++;
+ return (u->inp_curr = u->inp_buf[u->inp_buf_index++]);
+ }
+ } else {
+ int c = u->inp_peek;
+ if (c != UD_EOI || (c = u->inp_hook(u)) != UD_EOI) {
+ u->inp_peek = UD_EOI;
+ u->inp_curr = c;
+ u->inp_sess[u->inp_ctr++] = u->inp_curr;
+ return u->inp_curr;
+ }
+ }
+ }
+ u->inp_end = 1;
+ UDERR(u, "byte expected, eoi received\n");
+ return 0;
+}
+
+static uint8_t
+inp_curr(struct ud *u)
+{
+ return u->inp_curr;
+}
+
+
+/*
+ * inp_uint8
+ * int_uint16
+ * int_uint32
+ * int_uint64
+ * Load little-endian values from input
+ */
+static uint8_t
+inp_uint8(struct ud* u)
+{
+ return inp_next(u);
+}
+
+static uint16_t
+inp_uint16(struct ud* u)
+{
+ uint16_t r, ret;
+
+ ret = inp_next(u);
+ r = inp_next(u);
+ return ret | (r << 8);
+}
+
+static uint32_t
+inp_uint32(struct ud* u)
+{
+ uint32_t r, ret;
+
+ ret = inp_next(u);
+ r = inp_next(u);
+ ret = ret | (r << 8);
+ r = inp_next(u);
+ ret = ret | (r << 16);
+ r = inp_next(u);
+ return ret | (r << 24);
+}
+
+static uint64_t
+inp_uint64(struct ud* u)
+{
+ uint64_t r, ret;
+
+ ret = inp_next(u);
+ r = inp_next(u);
+ ret = ret | (r << 8);
+ r = inp_next(u);
+ ret = ret | (r << 16);
+ r = inp_next(u);
+ ret = ret | (r << 24);
+ r = inp_next(u);
+ ret = ret | (r << 32);
+ r = inp_next(u);
+ ret = ret | (r << 40);
+ r = inp_next(u);
+ ret = ret | (r << 48);
+ r = inp_next(u);
+ return ret | (r << 56);
+}
+
+
+static UD_INLINE int
</ins><span class="cx"> eff_opr_mode(int dis_mode, int rex_w, int pfx_opr)
</span><span class="cx"> {
</span><span class="cx"> if (dis_mode == 64) {
</span><span class="lines">@@ -60,13 +205,13 @@
</span><span class="cx"> } else if (dis_mode == 32) {
</span><span class="cx"> return pfx_opr ? 16 : 32;
</span><span class="cx"> } else {
</span><del>- ASSERT(dis_mode == 16);
</del><ins>+ UD_ASSERT(dis_mode == 16);
</ins><span class="cx"> return pfx_opr ? 32 : 16;
</span><span class="cx"> }
</span><span class="cx"> }
</span><span class="cx">
</span><span class="cx">
</span><del>-static inline int
</del><ins>+static UD_INLINE int
</ins><span class="cx"> eff_adr_mode(int dis_mode, int pfx_adr)
</span><span class="cx"> {
</span><span class="cx"> if (dis_mode == 64) {
</span><span class="lines">@@ -74,21 +219,12 @@
</span><span class="cx"> } else if (dis_mode == 32) {
</span><span class="cx"> return pfx_adr ? 16 : 32;
</span><span class="cx"> } else {
</span><del>- ASSERT(dis_mode == 16);
</del><ins>+ UD_ASSERT(dis_mode == 16);
</ins><span class="cx"> return pfx_adr ? 32 : 16;
</span><span class="cx"> }
</span><span class="cx"> }
</span><span class="cx">
</span><span class="cx">
</span><del>-/* Looks up mnemonic code in the mnemonic string table
- * Returns NULL if the mnemonic code is invalid
- */
-const char * ud_lookup_mnemonic( enum ud_mnemonic_code c )
-{
- return ud_mnemonics_str[ c ];
-}
-
-
</del><span class="cx"> /*
</span><span class="cx"> * decode_prefixes
</span><span class="cx"> *
</span><span class="lines">@@ -97,164 +233,128 @@
</span><span class="cx"> static int
</span><span class="cx"> decode_prefixes(struct ud *u)
</span><span class="cx"> {
</span><del>- unsigned int have_pfx = 1;
- unsigned int i;
- uint8_t curr;
</del><ins>+ int done = 0;
+ uint8_t curr = 0, last = 0;
+ UD_RETURN_ON_ERROR(u);
</ins><span class="cx">
</span><del>- /* if in error state, bail out */
- if ( u->error )
- return -1;
-
- /* keep going as long as there are prefixes available */
- for ( i = 0; have_pfx ; ++i ) {
-
- /* Get next byte. */
- ud_inp_next(u);
- if ( u->error )
- return -1;
- curr = ud_inp_curr( u );
-
- /* rex prefixes in 64bit mode */
- if ( u->dis_mode == 64 && ( curr & 0xF0 ) == 0x40 ) {
- u->pfx_rex = curr;
- } else {
- switch ( curr )
- {
- case 0x2E :
- u->pfx_seg = UD_R_CS;
- u->pfx_rex = 0;
- break;
- case 0x36 :
- u->pfx_seg = UD_R_SS;
- u->pfx_rex = 0;
- break;
- case 0x3E :
- u->pfx_seg = UD_R_DS;
- u->pfx_rex = 0;
- break;
- case 0x26 :
- u->pfx_seg = UD_R_ES;
- u->pfx_rex = 0;
- break;
- case 0x64 :
- u->pfx_seg = UD_R_FS;
- u->pfx_rex = 0;
- break;
- case 0x65 :
- u->pfx_seg = UD_R_GS;
- u->pfx_rex = 0;
- break;
- case 0x67 : /* adress-size override prefix */
- u->pfx_adr = 0x67;
- u->pfx_rex = 0;
- break;
- case 0xF0 :
- u->pfx_lock = 0xF0;
- u->pfx_rex = 0;
- break;
- case 0x66:
- /* the 0x66 sse prefix is only effective if no other sse prefix
- * has already been specified.
- */
- if ( !u->pfx_insn ) u->pfx_insn = 0x66;
- u->pfx_opr = 0x66;
- u->pfx_rex = 0;
- break;
- case 0xF2:
- u->pfx_insn = 0xF2;
- u->pfx_repne = 0xF2;
- u->pfx_rex = 0;
- break;
- case 0xF3:
- u->pfx_insn = 0xF3;
- u->pfx_rep = 0xF3;
- u->pfx_repe = 0xF3;
- u->pfx_rex = 0;
- break;
- default :
- /* No more prefixes */
- have_pfx = 0;
- break;
- }
- }
-
- /* check if we reached max instruction length */
- if ( i + 1 == MAX_INSN_LENGTH ) {
- u->error = 1;
- break;
- }
</del><ins>+ do {
+ last = curr;
+ curr = inp_next(u);
+ UD_RETURN_ON_ERROR(u);
+ if (u->inp_ctr == MAX_INSN_LENGTH) {
+ UD_RETURN_WITH_ERROR(u, "max instruction length");
</ins><span class="cx"> }
</span><ins>+
+ switch (curr)
+ {
+ case 0x2E:
+ u->pfx_seg = UD_R_CS;
+ break;
+ case 0x36:
+ u->pfx_seg = UD_R_SS;
+ break;
+ case 0x3E:
+ u->pfx_seg = UD_R_DS;
+ break;
+ case 0x26:
+ u->pfx_seg = UD_R_ES;
+ break;
+ case 0x64:
+ u->pfx_seg = UD_R_FS;
+ break;
+ case 0x65:
+ u->pfx_seg = UD_R_GS;
+ break;
+ case 0x67: /* adress-size override prefix */
+ u->pfx_adr = 0x67;
+ break;
+ case 0xF0:
+ u->pfx_lock = 0xF0;
+ break;
+ case 0x66:
+ u->pfx_opr = 0x66;
+ break;
+ case 0xF2:
+ u->pfx_str = 0xf2;
+ break;
+ case 0xF3:
+ u->pfx_str = 0xf3;
+ break;
+ default:
+ /* consume if rex */
+ done = (u->dis_mode == 64 && (curr & 0xF0) == 0x40) ? 0 : 1;
+ break;
+ }
+ } while (!done);
+ /* rex prefixes in 64bit mode, must be the last prefix */
+ if (u->dis_mode == 64 && (last & 0xF0) == 0x40) {
+ u->pfx_rex = last;
+ }
+ return 0;
+}
</ins><span class="cx">
</span><del>- /* return status */
- if ( u->error )
- return -1;
</del><span class="cx">
</span><del>- /* rewind back one byte in stream, since the above loop
- * stops with a non-prefix byte.
- */
- ud_inp_back(u);
- return 0;
</del><ins>+/*
+ * vex_l, vex_w
+ * Return the vex.L and vex.W bits
+ */
+static UD_INLINE uint8_t
+vex_l(const struct ud *u)
+{
+ UD_ASSERT(u->vex_op != 0);
+ return ((u->vex_op == 0xc4 ? u->vex_b2 : u->vex_b1) >> 2) & 1;
</ins><span class="cx"> }
</span><span class="cx">
</span><ins>+static UD_INLINE uint8_t
+vex_w(const struct ud *u)
+{
+ UD_ASSERT(u->vex_op != 0);
+ return u->vex_op == 0xc4 ? ((u->vex_b2 >> 7) & 1) : 0;
+}
</ins><span class="cx">
</span><del>-static inline unsigned int modrm( struct ud * u )
</del><ins>+
+static UD_INLINE uint8_t
+modrm(struct ud * u)
</ins><span class="cx"> {
</span><span class="cx"> if ( !u->have_modrm ) {
</span><del>- u->modrm = ud_inp_next( u );
</del><ins>+ u->modrm = inp_next( u );
+ u->modrm_offset = (uint8_t) (u->inp_ctr - 1);
</ins><span class="cx"> u->have_modrm = 1;
</span><span class="cx"> }
</span><span class="cx"> return u->modrm;
</span><span class="cx"> }
</span><span class="cx">
</span><span class="cx">
</span><del>-static unsigned int resolve_operand_size( const struct ud * u, unsigned int s )
</del><ins>+static unsigned int
+resolve_operand_size(const struct ud* u, ud_operand_size_t osize)
</ins><span class="cx"> {
</span><del>- switch ( s )
- {
- case SZ_V:
- return ( u->opr_mode );
- case SZ_Z:
- return ( u->opr_mode == 16 ) ? 16 : 32;
- case SZ_P:
- return ( u->opr_mode == 16 ) ? SZ_WP : SZ_DP;
- case SZ_MDQ:
- return ( u->opr_mode == 16 ) ? 32 : u->opr_mode;
- case SZ_RDQ:
- return ( u->dis_mode == 64 ) ? 64 : 32;
- default:
- return s;
- }
</del><ins>+ switch (osize) {
+ case SZ_V:
+ return u->opr_mode;
+ case SZ_Z:
+ return u->opr_mode == 16 ? 16 : 32;
+ case SZ_Y:
+ return u->opr_mode == 16 ? 32 : u->opr_mode;
+ case SZ_RDQ:
+ return u->dis_mode == 64 ? 64 : 32;
+ case SZ_X:
+ UD_ASSERT(u->vex_op != 0);
+ return (P_VEXL(u->itab_entry->prefix) && vex_l(u)) ? SZ_QQ : SZ_DQ;
+ default:
+ return osize;
+ }
</ins><span class="cx"> }
</span><span class="cx">
</span><span class="cx">
</span><span class="cx"> static int resolve_mnemonic( struct ud* u )
</span><span class="cx"> {
</span><del>- /* far/near flags */
- u->br_far = 0;
- u->br_near = 0;
- /* readjust operand sizes for call/jmp instrcutions */
- if ( u->mnemonic == UD_Icall || u->mnemonic == UD_Ijmp ) {
- /* WP: 16:16 pointer */
- if ( u->operand[ 0 ].size == SZ_WP ) {
- u->operand[ 0 ].size = 16;
- u->br_far = 1;
- u->br_near= 0;
- /* DP: 32:32 pointer */
- } else if ( u->operand[ 0 ].size == SZ_DP ) {
- u->operand[ 0 ].size = 32;
- u->br_far = 1;
- u->br_near= 0;
- } else {
- u->br_far = 0;
- u->br_near= 1;
- }
</del><span class="cx"> /* resolve 3dnow weirdness. */
</span><del>- } else if ( u->mnemonic == UD_I3dnow ) {
- u->mnemonic = ud_itab[ u->le->table[ ud_inp_curr( u ) ] ].mnemonic;
</del><ins>+ if ( u->mnemonic == UD_I3dnow ) {
+ u->mnemonic = ud_itab[ u->le->table[ inp_curr( u ) ] ].mnemonic;
</ins><span class="cx"> }
</span><span class="cx"> /* SWAPGS is only valid in 64bits mode */
</span><span class="cx"> if ( u->mnemonic == UD_Iswapgs && u->dis_mode != 64 ) {
</span><del>- u->error = 1;
</del><ins>+ UDERR(u, "swapgs invalid in 64bits mode\n");
</ins><span class="cx"> return -1;
</span><span class="cx"> }
</span><span class="cx">
</span><span class="lines">@@ -269,8 +369,8 @@
</span><span class="cx"> }
</span><span class="cx"> }
</span><span class="cx">
</span><del>- if (u->mnemonic == UD_Inop && u->pfx_rep) {
- u->pfx_rep = 0;
</del><ins>+ if (u->mnemonic == UD_Inop && u->pfx_repe) {
+ u->pfx_repe = 0;
</ins><span class="cx"> u->mnemonic = UD_Ipause;
</span><span class="cx"> }
</span><span class="cx"> return 0;
</span><span class="lines">@@ -288,14 +388,14 @@
</span><span class="cx"> /* seg16:off16 */
</span><span class="cx"> op->type = UD_OP_PTR;
</span><span class="cx"> op->size = 32;
</span><del>- op->lval.ptr.off = ud_inp_uint16(u);
- op->lval.ptr.seg = ud_inp_uint16(u);
</del><ins>+ op->lval.ptr.off = inp_uint16(u);
+ op->lval.ptr.seg = inp_uint16(u);
</ins><span class="cx"> } else {
</span><span class="cx"> /* seg16:off32 */
</span><span class="cx"> op->type = UD_OP_PTR;
</span><span class="cx"> op->size = 48;
</span><del>- op->lval.ptr.off = ud_inp_uint32(u);
- op->lval.ptr.seg = ud_inp_uint16(u);
</del><ins>+ op->lval.ptr.off = inp_uint32(u);
+ op->lval.ptr.seg = inp_uint16(u);
</ins><span class="cx"> }
</span><span class="cx"> }
</span><span class="cx">
</span><span class="lines">@@ -306,15 +406,11 @@
</span><span class="cx"> static enum ud_type
</span><span class="cx"> decode_gpr(register struct ud* u, unsigned int s, unsigned char rm)
</span><span class="cx"> {
</span><del>- s = resolve_operand_size(u, s);
-
</del><span class="cx"> switch (s) {
</span><span class="cx"> case 64:
</span><span class="cx"> return UD_R_RAX + rm;
</span><del>- case SZ_DP:
</del><span class="cx"> case 32:
</span><span class="cx"> return UD_R_EAX + rm;
</span><del>- case SZ_WP:
</del><span class="cx"> case 16:
</span><span class="cx"> return UD_R_AX + rm;
</span><span class="cx"> case 8:
</span><span class="lines">@@ -323,119 +419,121 @@
</span><span class="cx"> return UD_R_SPL + (rm-4);
</span><span class="cx"> return UD_R_AL + rm;
</span><span class="cx"> } else return UD_R_AL + rm;
</span><ins>+ case 0:
+ /* invalid size in case of a decode error */
+ UD_ASSERT(u->error);
+ return UD_NONE;
</ins><span class="cx"> default:
</span><del>- return 0;
</del><ins>+ UD_ASSERT(!"invalid operand size");
+ return UD_NONE;
</ins><span class="cx"> }
</span><span class="cx"> }
</span><span class="cx">
</span><del>-/* -----------------------------------------------------------------------------
- * resolve_gpr64() - 64bit General Purpose Register-Selection.
- * -----------------------------------------------------------------------------
- */
-static enum ud_type
-resolve_gpr64(struct ud* u, enum ud_operand_code gpr_op, enum ud_operand_size * size)
</del><ins>+static void
+decode_reg(struct ud *u,
+ struct ud_operand *opr,
+ int type,
+ int num,
+ int size)
</ins><span class="cx"> {
</span><del>- if (gpr_op >= OP_rAXr8 && gpr_op <= OP_rDIr15)
- gpr_op = (gpr_op - OP_rAXr8) | (REX_B(u->pfx_rex) << 3);
- else gpr_op = (gpr_op - OP_rAX);
-
- if (u->opr_mode == 16) {
- *size = 16;
- return gpr_op + UD_R_AX;
- }
- if (u->dis_mode == 32 ||
- (u->opr_mode == 32 && ! (REX_W(u->pfx_rex) || u->default64))) {
- *size = 32;
- return gpr_op + UD_R_EAX;
- }
-
- *size = 64;
- return gpr_op + UD_R_RAX;
-}
-
-/* -----------------------------------------------------------------------------
- * resolve_gpr32 () - 32bit General Purpose Register-Selection.
- * -----------------------------------------------------------------------------
- */
-static enum ud_type
-resolve_gpr32(struct ud* u, enum ud_operand_code gpr_op)
-{
- gpr_op = gpr_op - OP_eAX;
-
- if (u->opr_mode == 16)
- return gpr_op + UD_R_AX;
-
- return gpr_op + UD_R_EAX;
-}
-
-/* -----------------------------------------------------------------------------
- * resolve_reg() - Resolves the register type
- * -----------------------------------------------------------------------------
- */
-static enum ud_type
-resolve_reg(struct ud* u, unsigned int type, unsigned char i)
-{
</del><ins>+ int reg;
+ size = resolve_operand_size(u, size);
</ins><span class="cx"> switch (type) {
</span><del>- case T_MMX : return UD_R_MM0 + (i & 7);
- case T_XMM : return UD_R_XMM0 + i;
- case T_CRG : return UD_R_CR0 + i;
- case T_DBG : return UD_R_DR0 + i;
- case T_SEG : {
</del><ins>+ case REGCLASS_GPR : reg = decode_gpr(u, size, num); break;
+ case REGCLASS_MMX : reg = UD_R_MM0 + (num & 7); break;
+ case REGCLASS_XMM :
+ reg = num + (size == SZ_QQ ? UD_R_YMM0 : UD_R_XMM0);
+ break;
+ case REGCLASS_CR : reg = UD_R_CR0 + num; break;
+ case REGCLASS_DB : reg = UD_R_DR0 + num; break;
+ case REGCLASS_SEG : {
</ins><span class="cx"> /*
</span><span class="cx"> * Only 6 segment registers, anything else is an error.
</span><span class="cx"> */
</span><del>- if ((i & 7) > 5) {
- u->error = 1;
</del><ins>+ if ((num & 7) > 5) {
+ UDERR(u, "invalid segment register value\n");
+ return;
</ins><span class="cx"> } else {
</span><del>- return UD_R_ES + (i & 7);
</del><ins>+ reg = UD_R_ES + (num & 7);
</ins><span class="cx"> }
</span><ins>+ break;
</ins><span class="cx"> }
</span><del>- case T_NONE:
- default: return UD_NONE;
</del><ins>+ default:
+ UD_ASSERT(!"invalid register type");
+ return;
</ins><span class="cx"> }
</span><ins>+ opr->type = UD_OP_REG;
+ opr->base = reg;
+ opr->size = size;
</ins><span class="cx"> }
</span><span class="cx">
</span><del>-/* -----------------------------------------------------------------------------
- * decode_imm() - Decodes Immediate values.
- * -----------------------------------------------------------------------------
</del><ins>+
+/*
+ * decode_imm
+ *
+ * Decode Immediate values.
</ins><span class="cx"> */
</span><span class="cx"> static void
</span><del>-decode_imm(struct ud* u, unsigned int s, struct ud_operand *op)
</del><ins>+decode_imm(struct ud* u, unsigned int size, struct ud_operand *op)
</ins><span class="cx"> {
</span><del>- op->size = resolve_operand_size(u, s);
</del><ins>+ op->size = resolve_operand_size(u, size);
</ins><span class="cx"> op->type = UD_OP_IMM;
</span><span class="cx">
</span><span class="cx"> switch (op->size) {
</span><del>- case 8: op->lval.sbyte = ud_inp_uint8(u); break;
- case 16: op->lval.uword = ud_inp_uint16(u); break;
- case 32: op->lval.udword = ud_inp_uint32(u); break;
- case 64: op->lval.uqword = ud_inp_uint64(u); break;
- default: return;
</del><ins>+ case 8: op->lval.sbyte = inp_uint8(u); break;
+ case 16: op->lval.uword = inp_uint16(u); break;
+ case 32: op->lval.udword = inp_uint32(u); break;
+ case 64: op->lval.uqword = inp_uint64(u); break;
+ default: return;
</ins><span class="cx"> }
</span><span class="cx"> }
</span><span class="cx">
</span><span class="cx">
</span><ins>+/*
+ * decode_mem_disp
+ *
+ * Decode mem address displacement.
+ */
+static void
+decode_mem_disp(struct ud* u, unsigned int size, struct ud_operand *op)
+{
+ switch (size) {
+ case 8:
+ op->offset = 8;
+ op->lval.ubyte = inp_uint8(u);
+ break;
+ case 16:
+ op->offset = 16;
+ op->lval.uword = inp_uint16(u);
+ break;
+ case 32:
+ op->offset = 32;
+ op->lval.udword = inp_uint32(u);
+ break;
+ case 64:
+ op->offset = 64;
+ op->lval.uqword = inp_uint64(u);
+ break;
+ default:
+ return;
+ }
+}
+
+
</ins><span class="cx"> /*
</span><span class="cx"> * decode_modrm_reg
</span><span class="cx"> *
</span><span class="cx"> * Decodes reg field of mod/rm byte
</span><span class="cx"> *
</span><span class="cx"> */
</span><del>-static void
</del><ins>+static UD_INLINE void
</ins><span class="cx"> decode_modrm_reg(struct ud *u,
</span><span class="cx"> struct ud_operand *operand,
</span><span class="cx"> unsigned int type,
</span><span class="cx"> unsigned int size)
</span><span class="cx"> {
</span><del>- uint8_t reg = (REX_R(u->pfx_rex) << 3) | MODRM_REG(modrm(u));
- operand->type = UD_OP_REG;
- operand->size = resolve_operand_size(u, size);
-
- if (type == T_GPR) {
- operand->base = decode_gpr(u, operand->size, reg);
- } else {
- operand->base = resolve_reg(u, type, reg);
- }
</del><ins>+ uint8_t reg = (REX_R(u->_rex) << 3) | MODRM_REG(modrm(u));
+ decode_reg(u, operand, type, reg, size);
</ins><span class="cx"> }
</span><span class="cx">
</span><span class="cx">
</span><span class="lines">@@ -448,67 +546,58 @@
</span><span class="cx"> static void
</span><span class="cx"> decode_modrm_rm(struct ud *u,
</span><span class="cx"> struct ud_operand *op,
</span><del>- unsigned char type,
- unsigned int size)
</del><ins>+ unsigned char type, /* register type */
+ unsigned int size) /* operand size */
</ins><span class="cx">
</span><span class="cx"> {
</span><del>- unsigned char mod, rm, reg;
</del><ins>+ size_t offset = 0;
+ unsigned char mod, rm;
</ins><span class="cx">
</span><span class="cx"> /* get mod, r/m and reg fields */
</span><span class="cx"> mod = MODRM_MOD(modrm(u));
</span><del>- rm = (REX_B(u->pfx_rex) << 3) | MODRM_RM(modrm(u));
- reg = (REX_R(u->pfx_rex) << 3) | MODRM_REG(modrm(u));
</del><ins>+ rm = (REX_B(u->_rex) << 3) | MODRM_RM(modrm(u));
</ins><span class="cx">
</span><del>- UNUSED_PARAM(reg);
-
- op->size = resolve_operand_size(u, size);
-
</del><span class="cx"> /*
</span><span class="cx"> * If mod is 11b, then the modrm.rm specifies a register.
</span><span class="cx"> *
</span><span class="cx"> */
</span><span class="cx"> if (mod == 3) {
</span><del>- op->type = UD_OP_REG;
- if (type == T_GPR) {
- op->base = decode_gpr(u, op->size, rm);
- } else {
- op->base = resolve_reg(u, type, (REX_B(u->pfx_rex) << 3) | (rm & 7));
- }
</del><ins>+ decode_reg(u, op, type, rm, size);
</ins><span class="cx"> return;
</span><del>- }
</del><ins>+ }
</ins><span class="cx">
</span><del>-
</del><span class="cx"> /*
</span><del>- * !11 => Memory Address
</del><ins>+ * !11b => Memory Address
</ins><span class="cx"> */
</span><span class="cx"> op->type = UD_OP_MEM;
</span><ins>+ op->size = resolve_operand_size(u, size);
</ins><span class="cx">
</span><span class="cx"> if (u->adr_mode == 64) {
</span><span class="cx"> op->base = UD_R_RAX + rm;
</span><span class="cx"> if (mod == 1) {
</span><del>- op->offset = 8;
</del><ins>+ offset = 8;
</ins><span class="cx"> } else if (mod == 2) {
</span><del>- op->offset = 32;
</del><ins>+ offset = 32;
</ins><span class="cx"> } else if (mod == 0 && (rm & 7) == 5) {
</span><span class="cx"> op->base = UD_R_RIP;
</span><del>- op->offset = 32;
</del><ins>+ offset = 32;
</ins><span class="cx"> } else {
</span><del>- op->offset = 0;
</del><ins>+ offset = 0;
</ins><span class="cx"> }
</span><span class="cx"> /*
</span><span class="cx"> * Scale-Index-Base (SIB)
</span><span class="cx"> */
</span><span class="cx"> if ((rm & 7) == 4) {
</span><del>- ud_inp_next(u);
</del><ins>+ inp_next(u);
</ins><span class="cx">
</span><del>- op->scale = (1 << SIB_S(ud_inp_curr(u))) & ~1;
- op->index = UD_R_RAX + (SIB_I(ud_inp_curr(u)) | (REX_X(u->pfx_rex) << 3));
- op->base = UD_R_RAX + (SIB_B(ud_inp_curr(u)) | (REX_B(u->pfx_rex) << 3));
-
</del><ins>+ op->base = UD_R_RAX + (SIB_B(inp_curr(u)) | (REX_B(u->_rex) << 3));
+ op->index = UD_R_RAX + (SIB_I(inp_curr(u)) | (REX_X(u->_rex) << 3));
</ins><span class="cx"> /* special conditions for base reference */
</span><span class="cx"> if (op->index == UD_R_RSP) {
</span><span class="cx"> op->index = UD_NONE;
</span><span class="cx"> op->scale = UD_NONE;
</span><ins>+ } else {
+ op->scale = (1 << SIB_S(inp_curr(u))) & ~1;
</ins><span class="cx"> }
</span><span class="cx">
</span><span class="cx"> if (op->base == UD_R_RBP || op->base == UD_R_R13) {
</span><span class="lines">@@ -516,32 +605,35 @@
</span><span class="cx"> op->base = UD_NONE;
</span><span class="cx"> }
</span><span class="cx"> if (mod == 1) {
</span><del>- op->offset = 8;
</del><ins>+ offset = 8;
</ins><span class="cx"> } else {
</span><del>- op->offset = 32;
</del><ins>+ offset = 32;
</ins><span class="cx"> }
</span><span class="cx"> }
</span><ins>+ } else {
+ op->scale = UD_NONE;
+ op->index = UD_NONE;
</ins><span class="cx"> }
</span><span class="cx"> } else if (u->adr_mode == 32) {
</span><span class="cx"> op->base = UD_R_EAX + rm;
</span><span class="cx"> if (mod == 1) {
</span><del>- op->offset = 8;
</del><ins>+ offset = 8;
</ins><span class="cx"> } else if (mod == 2) {
</span><del>- op->offset = 32;
</del><ins>+ offset = 32;
</ins><span class="cx"> } else if (mod == 0 && rm == 5) {
</span><span class="cx"> op->base = UD_NONE;
</span><del>- op->offset = 32;
</del><ins>+ offset = 32;
</ins><span class="cx"> } else {
</span><del>- op->offset = 0;
</del><ins>+ offset = 0;
</ins><span class="cx"> }
</span><span class="cx">
</span><span class="cx"> /* Scale-Index-Base (SIB) */
</span><span class="cx"> if ((rm & 7) == 4) {
</span><del>- ud_inp_next(u);
</del><ins>+ inp_next(u);
</ins><span class="cx">
</span><del>- op->scale = (1 << SIB_S(ud_inp_curr(u))) & ~1;
- op->index = UD_R_EAX + (SIB_I(ud_inp_curr(u)) | (REX_X(u->pfx_rex) << 3));
- op->base = UD_R_EAX + (SIB_B(ud_inp_curr(u)) | (REX_B(u->pfx_rex) << 3));
</del><ins>+ op->scale = (1 << SIB_S(inp_curr(u))) & ~1;
+ op->index = UD_R_EAX + (SIB_I(inp_curr(u)) | (REX_X(u->pfx_rex) << 3));
+ op->base = UD_R_EAX + (SIB_B(inp_curr(u)) | (REX_B(u->pfx_rex) << 3));
</ins><span class="cx">
</span><span class="cx"> if (op->index == UD_R_ESP) {
</span><span class="cx"> op->index = UD_NONE;
</span><span class="lines">@@ -554,11 +646,14 @@
</span><span class="cx"> op->base = UD_NONE;
</span><span class="cx"> }
</span><span class="cx"> if (mod == 1) {
</span><del>- op->offset = 8;
</del><ins>+ offset = 8;
</ins><span class="cx"> } else {
</span><del>- op->offset = 32;
</del><ins>+ offset = 32;
</ins><span class="cx"> }
</span><span class="cx"> }
</span><ins>+ } else {
+ op->scale = UD_NONE;
+ op->index = UD_NONE;
</ins><span class="cx"> }
</span><span class="cx"> } else {
</span><span class="cx"> const unsigned int bases[] = { UD_R_BX, UD_R_BX, UD_R_BP, UD_R_BP,
</span><span class="lines">@@ -567,94 +662,106 @@
</span><span class="cx"> UD_NONE, UD_NONE, UD_NONE, UD_NONE };
</span><span class="cx"> op->base = bases[rm & 7];
</span><span class="cx"> op->index = indices[rm & 7];
</span><ins>+ op->scale = UD_NONE;
</ins><span class="cx"> if (mod == 0 && rm == 6) {
</span><del>- op->offset= 16;
</del><ins>+ offset = 16;
</ins><span class="cx"> op->base = UD_NONE;
</span><span class="cx"> } else if (mod == 1) {
</span><del>- op->offset = 8;
</del><ins>+ offset = 8;
</ins><span class="cx"> } else if (mod == 2) {
</span><del>- op->offset = 16;
</del><ins>+ offset = 16;
</ins><span class="cx"> }
</span><span class="cx"> }
</span><span class="cx">
</span><del>- /*
- * extract offset, if any
- */
- switch (op->offset) {
- case 8 : op->lval.ubyte = ud_inp_uint8(u); break;
- case 16: op->lval.uword = ud_inp_uint16(u); break;
- case 32: op->lval.udword = ud_inp_uint32(u); break;
- case 64: op->lval.uqword = ud_inp_uint64(u); break;
- default: break;
</del><ins>+ if (offset) {
+ decode_mem_disp(u, offset, op);
+ } else {
+ op->offset = 0;
</ins><span class="cx"> }
</span><span class="cx"> }
</span><span class="cx">
</span><del>-/* -----------------------------------------------------------------------------
- * decode_o() - Decodes offset
- * -----------------------------------------------------------------------------
</del><ins>+
+/*
+ * decode_moffset
+ * Decode offset-only memory operand
</ins><span class="cx"> */
</span><del>-static void
-decode_o(struct ud* u, unsigned int s, struct ud_operand *op)
</del><ins>+static void
+decode_moffset(struct ud *u, unsigned int size, struct ud_operand *opr)
</ins><span class="cx"> {
</span><del>- switch (u->adr_mode) {
- case 64:
- op->offset = 64;
- op->lval.uqword = ud_inp_uint64(u);
- break;
- case 32:
- op->offset = 32;
- op->lval.udword = ud_inp_uint32(u);
- break;
- case 16:
- op->offset = 16;
- op->lval.uword = ud_inp_uint16(u);
- break;
- default:
- return;
- }
- op->type = UD_OP_MEM;
- op->size = resolve_operand_size(u, s);
</del><ins>+ opr->type = UD_OP_MEM;
+ opr->base = UD_NONE;
+ opr->index = UD_NONE;
+ opr->scale = UD_NONE;
+ opr->size = resolve_operand_size(u, size);
+ decode_mem_disp(u, u->adr_mode, opr);
</ins><span class="cx"> }
</span><span class="cx">
</span><del>-/* -----------------------------------------------------------------------------
- * decode_operands() - Disassembles Operands.
- * -----------------------------------------------------------------------------
</del><ins>+
+static void
+decode_vex_vvvv(struct ud *u, struct ud_operand *opr, unsigned size)
+{
+ uint8_t vvvv;
+ UD_ASSERT(u->vex_op != 0);
+ vvvv = ((u->vex_op == 0xc4 ? u->vex_b2 : u->vex_b1) >> 3) & 0xf;
+ decode_reg(u, opr, REGCLASS_XMM, (0xf & ~vvvv), size);
+}
+
+
+/*
+ * decode_vex_immreg
+ * Decode source operand encoded in immediate byte [7:4]
</ins><span class="cx"> */
</span><span class="cx"> static int
</span><ins>+decode_vex_immreg(struct ud *u, struct ud_operand *opr, unsigned size)
+{
+ uint8_t imm = inp_next(u);
+ uint8_t mask = u->dis_mode == 64 ? 0xf : 0x7;
+ UD_RETURN_ON_ERROR(u);
+ UD_ASSERT(u->vex_op != 0);
+ decode_reg(u, opr, REGCLASS_XMM, mask & (imm >> 4), size);
+ return 0;
+}
+
+
+/*
+ * decode_operand
+ *
+ * Decodes a single operand.
+ * Returns the type of the operand (UD_NONE if none)
+ */
+static int
</ins><span class="cx"> decode_operand(struct ud *u,
</span><span class="cx"> struct ud_operand *operand,
</span><span class="cx"> enum ud_operand_code type,
</span><span class="cx"> unsigned int size)
</span><span class="cx"> {
</span><ins>+ operand->type = UD_NONE;
+ operand->_oprcode = type;
+
</ins><span class="cx"> switch (type) {
</span><span class="cx"> case OP_A :
</span><span class="cx"> decode_a(u, operand);
</span><span class="cx"> break;
</span><span class="cx"> case OP_MR:
</span><del>- if (MODRM_MOD(modrm(u)) == 3) {
- decode_modrm_rm(u, operand, T_GPR,
- size == SZ_DY ? SZ_MDQ : SZ_V);
- } else if (size == SZ_WV) {
- decode_modrm_rm( u, operand, T_GPR, SZ_W);
- } else if (size == SZ_BV) {
- decode_modrm_rm( u, operand, T_GPR, SZ_B);
- } else if (size == SZ_DY) {
- decode_modrm_rm( u, operand, T_GPR, SZ_D);
- } else {
- ASSERT(!"unexpected size");
- }
</del><ins>+ decode_modrm_rm(u, operand, REGCLASS_GPR,
+ MODRM_MOD(modrm(u)) == 3 ?
+ Mx_reg_size(size) : Mx_mem_size(size));
</ins><span class="cx"> break;
</span><ins>+ case OP_F:
+ u->br_far = 1;
+ /* intended fall through */
</ins><span class="cx"> case OP_M:
</span><span class="cx"> if (MODRM_MOD(modrm(u)) == 3) {
</span><del>- u->error = 1;
</del><ins>+ UDERR(u, "expected modrm.mod != 3\n");
</ins><span class="cx"> }
</span><span class="cx"> /* intended fall through */
</span><span class="cx"> case OP_E:
</span><del>- decode_modrm_rm(u, operand, T_GPR, size);
</del><ins>+ decode_modrm_rm(u, operand, REGCLASS_GPR, size);
</ins><span class="cx"> break;
</span><span class="cx"> case OP_G:
</span><del>- decode_modrm_reg(u, operand, T_GPR, size);
</del><ins>+ decode_modrm_reg(u, operand, REGCLASS_GPR, size);
</ins><span class="cx"> break;
</span><ins>+ case OP_sI:
</ins><span class="cx"> case OP_I:
</span><span class="cx"> decode_imm(u, size, operand);
</span><span class="cx"> break;
</span><span class="lines">@@ -662,97 +769,69 @@
</span><span class="cx"> operand->type = UD_OP_CONST;
</span><span class="cx"> operand->lval.udword = 1;
</span><span class="cx"> break;
</span><del>- case OP_PR:
</del><ins>+ case OP_N:
</ins><span class="cx"> if (MODRM_MOD(modrm(u)) != 3) {
</span><del>- u->error = 1;
</del><ins>+ UDERR(u, "expected modrm.mod == 3\n");
</ins><span class="cx"> }
</span><del>- decode_modrm_rm(u, operand, T_MMX, size);
</del><ins>+ /* intended fall through */
+ case OP_Q:
+ decode_modrm_rm(u, operand, REGCLASS_MMX, size);
</ins><span class="cx"> break;
</span><span class="cx"> case OP_P:
</span><del>- decode_modrm_reg(u, operand, T_MMX, size);
</del><ins>+ decode_modrm_reg(u, operand, REGCLASS_MMX, size);
</ins><span class="cx"> break;
</span><del>- case OP_VR:
</del><ins>+ case OP_U:
</ins><span class="cx"> if (MODRM_MOD(modrm(u)) != 3) {
</span><del>- u->error = 1;
</del><ins>+ UDERR(u, "expected modrm.mod == 3\n");
</ins><span class="cx"> }
</span><span class="cx"> /* intended fall through */
</span><span class="cx"> case OP_W:
</span><del>- decode_modrm_rm(u, operand, T_XMM, size);
</del><ins>+ decode_modrm_rm(u, operand, REGCLASS_XMM, size);
</ins><span class="cx"> break;
</span><span class="cx"> case OP_V:
</span><del>- decode_modrm_reg(u, operand, T_XMM, size);
</del><ins>+ decode_modrm_reg(u, operand, REGCLASS_XMM, size);
</ins><span class="cx"> break;
</span><del>- case OP_S:
- decode_modrm_reg(u, operand, T_SEG, size);
</del><ins>+ case OP_H:
+ decode_vex_vvvv(u, operand, size);
</ins><span class="cx"> break;
</span><del>- case OP_AL:
- case OP_CL:
- case OP_DL:
- case OP_BL:
- case OP_AH:
- case OP_CH:
- case OP_DH:
- case OP_BH:
- operand->type = UD_OP_REG;
- operand->base = UD_R_AL + (type - OP_AL);
- operand->size = 8;
</del><ins>+ case OP_MU:
+ decode_modrm_rm(u, operand, REGCLASS_XMM,
+ MODRM_MOD(modrm(u)) == 3 ?
+ Mx_reg_size(size) : Mx_mem_size(size));
</ins><span class="cx"> break;
</span><del>- case OP_DX:
- operand->type = UD_OP_REG;
- operand->base = UD_R_DX;
- operand->size = 16;
</del><ins>+ case OP_S:
+ decode_modrm_reg(u, operand, REGCLASS_SEG, size);
</ins><span class="cx"> break;
</span><span class="cx"> case OP_O:
</span><del>- decode_o(u, size, operand);
</del><ins>+ decode_moffset(u, size, operand);
</ins><span class="cx"> break;
</span><del>- case OP_rAXr8:
- case OP_rCXr9:
- case OP_rDXr10:
- case OP_rBXr11:
- case OP_rSPr12:
- case OP_rBPr13:
- case OP_rSIr14:
- case OP_rDIr15:
- case OP_rAX:
- case OP_rCX:
- case OP_rDX:
- case OP_rBX:
- case OP_rSP:
- case OP_rBP:
- case OP_rSI:
- case OP_rDI:
- operand->type = UD_OP_REG;
- operand->base = resolve_gpr64(u, type, &operand->size);
</del><ins>+ case OP_R0:
+ case OP_R1:
+ case OP_R2:
+ case OP_R3:
+ case OP_R4:
+ case OP_R5:
+ case OP_R6:
+ case OP_R7:
+ decode_reg(u, operand, REGCLASS_GPR,
+ (REX_B(u->_rex) << 3) | (type - OP_R0), size);
</ins><span class="cx"> break;
</span><del>- case OP_ALr8b:
- case OP_CLr9b:
- case OP_DLr10b:
- case OP_BLr11b:
- case OP_AHr12b:
- case OP_CHr13b:
- case OP_DHr14b:
- case OP_BHr15b: {
- ud_type_t gpr = (type - OP_ALr8b) + UD_R_AL
- + (REX_B(u->pfx_rex) << 3);
- if (UD_R_AH <= gpr && u->pfx_rex) {
- gpr = gpr + 4;
- }
- operand->type = UD_OP_REG;
- operand->base = gpr;
</del><ins>+ case OP_AL:
+ case OP_AX:
+ case OP_eAX:
+ case OP_rAX:
+ decode_reg(u, operand, REGCLASS_GPR, 0, size);
</ins><span class="cx"> break;
</span><del>- }
- case OP_eAX:
- case OP_eCX:
- case OP_eDX:
- case OP_eBX:
- case OP_eSP:
- case OP_eBP:
- case OP_eSI:
- case OP_eDI:
- operand->type = UD_OP_REG;
- operand->base = resolve_gpr32(u, type);
- operand->size = u->opr_mode == 16 ? 16 : 32;
</del><ins>+ case OP_CL:
+ case OP_CX:
+ case OP_eCX:
+ decode_reg(u, operand, REGCLASS_GPR, 1, size);
</ins><span class="cx"> break;
</span><ins>+ case OP_DL:
+ case OP_DX:
+ case OP_eDX:
+ decode_reg(u, operand, REGCLASS_GPR, 2, size);
+ break;
</ins><span class="cx"> case OP_ES:
</span><span class="cx"> case OP_CS:
</span><span class="cx"> case OP_DS:
</span><span class="lines">@@ -762,7 +841,7 @@
</span><span class="cx"> /* in 64bits mode, only fs and gs are allowed */
</span><span class="cx"> if (u->dis_mode == 64) {
</span><span class="cx"> if (type != OP_FS && type != OP_GS) {
</span><del>- u->error= 1;
</del><ins>+ UDERR(u, "invalid segment register in 64bits\n");
</ins><span class="cx"> }
</span><span class="cx"> }
</span><span class="cx"> operand->type = UD_OP_REG;
</span><span class="lines">@@ -773,17 +852,17 @@
</span><span class="cx"> decode_imm(u, size, operand);
</span><span class="cx"> operand->type = UD_OP_JIMM;
</span><span class="cx"> break ;
</span><del>- case OP_Q:
- decode_modrm_rm(u, operand, T_MMX, size);
- break;
</del><span class="cx"> case OP_R :
</span><del>- decode_modrm_rm(u, operand, T_GPR, size);
</del><ins>+ if (MODRM_MOD(modrm(u)) != 3) {
+ UDERR(u, "expected modrm.mod == 3\n");
+ }
+ decode_modrm_rm(u, operand, REGCLASS_GPR, size);
</ins><span class="cx"> break;
</span><span class="cx"> case OP_C:
</span><del>- decode_modrm_reg(u, operand, T_CRG, size);
</del><ins>+ decode_modrm_reg(u, operand, REGCLASS_CR, size);
</ins><span class="cx"> break;
</span><span class="cx"> case OP_D:
</span><del>- decode_modrm_reg(u, operand, T_DBG, size);
</del><ins>+ decode_modrm_reg(u, operand, REGCLASS_DB, size);
</ins><span class="cx"> break;
</span><span class="cx"> case OP_I3 :
</span><span class="cx"> operand->type = UD_OP_CONST;
</span><span class="lines">@@ -799,18 +878,16 @@
</span><span class="cx"> case OP_ST7:
</span><span class="cx"> operand->type = UD_OP_REG;
</span><span class="cx"> operand->base = (type - OP_ST0) + UD_R_ST0;
</span><del>- operand->size = 0;
</del><ins>+ operand->size = 80;
</ins><span class="cx"> break;
</span><del>- case OP_AX:
- operand->type = UD_OP_REG;
- operand->base = UD_R_AX;
- operand->size = 16;
</del><ins>+ case OP_L:
+ decode_vex_immreg(u, operand, size);
</ins><span class="cx"> break;
</span><span class="cx"> default :
</span><span class="cx"> operand->type = UD_NONE;
</span><span class="cx"> break;
</span><span class="cx"> }
</span><del>- return 0;
</del><ins>+ return operand->type;
</ins><span class="cx"> }
</span><span class="cx">
</span><span class="cx">
</span><span class="lines">@@ -827,12 +904,21 @@
</span><span class="cx"> decode_operand(u, &u->operand[0],
</span><span class="cx"> u->itab_entry->operand1.type,
</span><span class="cx"> u->itab_entry->operand1.size);
</span><del>- decode_operand(u, &u->operand[1],
- u->itab_entry->operand2.type,
- u->itab_entry->operand2.size);
- decode_operand(u, &u->operand[2],
- u->itab_entry->operand3.type,
- u->itab_entry->operand3.size);
</del><ins>+ if (u->operand[0].type != UD_NONE) {
+ decode_operand(u, &u->operand[1],
+ u->itab_entry->operand2.type,
+ u->itab_entry->operand2.size);
+ }
+ if (u->operand[1].type != UD_NONE) {
+ decode_operand(u, &u->operand[2],
+ u->itab_entry->operand3.type,
+ u->itab_entry->operand3.size);
+ }
+ if (u->operand[2].type != UD_NONE) {
+ decode_operand(u, &u->operand[3],
+ u->itab_entry->operand4.type,
+ u->itab_entry->operand4.size);
+ }
</ins><span class="cx"> return 0;
</span><span class="cx"> }
</span><span class="cx">
</span><span class="lines">@@ -852,19 +938,40 @@
</span><span class="cx"> u->pfx_rep = 0;
</span><span class="cx"> u->pfx_repe = 0;
</span><span class="cx"> u->pfx_rex = 0;
</span><del>- u->pfx_insn = 0;
</del><ins>+ u->pfx_str = 0;
</ins><span class="cx"> u->mnemonic = UD_Inone;
</span><span class="cx"> u->itab_entry = NULL;
</span><span class="cx"> u->have_modrm = 0;
</span><ins>+ u->br_far = 0;
+ u->vex_op = 0;
+ u->_rex = 0;
+ u->operand[0].type = UD_NONE;
+ u->operand[1].type = UD_NONE;
+ u->operand[2].type = UD_NONE;
+ u->operand[3].type = UD_NONE;
+}
</ins><span class="cx">
</span><del>- memset( &u->operand[ 0 ], 0, sizeof( struct ud_operand ) );
- memset( &u->operand[ 1 ], 0, sizeof( struct ud_operand ) );
- memset( &u->operand[ 2 ], 0, sizeof( struct ud_operand ) );
</del><ins>+
+static UD_INLINE int
+resolve_pfx_str(struct ud* u)
+{
+ if (u->pfx_str == 0xf3) {
+ if (P_STR(u->itab_entry->prefix)) {
+ u->pfx_rep = 0xf3;
+ } else {
+ u->pfx_repe = 0xf3;
+ }
+ } else if (u->pfx_str == 0xf2) {
+ u->pfx_repne = 0xf3;
+ }
+ return 0;
</ins><span class="cx"> }
</span><span class="cx">
</span><ins>+
</ins><span class="cx"> static int
</span><span class="cx"> resolve_mode( struct ud* u )
</span><span class="cx"> {
</span><ins>+ int default64;
</ins><span class="cx"> /* if in error state, bail out */
</span><span class="cx"> if ( u->error ) return -1;
</span><span class="cx">
</span><span class="lines">@@ -873,22 +980,34 @@
</span><span class="cx">
</span><span class="cx"> /* Check validity of instruction m64 */
</span><span class="cx"> if ( P_INV64( u->itab_entry->prefix ) ) {
</span><del>- u->error = 1;
- return -1;
</del><ins>+ UDERR(u, "instruction invalid in 64bits\n");
+ return -1;
</ins><span class="cx"> }
</span><span class="cx">
</span><del>- /* effective rex prefix is the effective mask for the
- * instruction hard-coded in the opcode map.
</del><ins>+ /* compute effective rex based on,
+ * - vex prefix (if any)
+ * - rex prefix (if any, and not vex)
+ * - allowed prefixes specified by the opcode map
</ins><span class="cx"> */
</span><del>- u->pfx_rex = ( u->pfx_rex & 0x40 ) |
- ( u->pfx_rex & REX_PFX_MASK( u->itab_entry->prefix ) );
</del><ins>+ if (u->vex_op == 0xc4) {
+ /* vex has rex.rxb in 1's complement */
+ u->_rex = ((~(u->vex_b1 >> 5) & 0x7) /* rex.0rxb */ |
+ ((u->vex_b2 >> 4) & 0x8) /* rex.w000 */);
+ } else if (u->vex_op == 0xc5) {
+ /* vex has rex.r in 1's complement */
+ u->_rex = (~(u->vex_b1 >> 5)) & 4;
+ } else {
+ UD_ASSERT(u->vex_op == 0);
+ u->_rex = u->pfx_rex;
+ }
+ u->_rex &= REX_PFX_MASK(u->itab_entry->prefix);
</ins><span class="cx">
</span><span class="cx"> /* whether this instruction has a default operand size of
</span><span class="cx"> * 64bit, also hardcoded into the opcode map.
</span><span class="cx"> */
</span><del>- u->default64 = P_DEF64( u->itab_entry->prefix );
</del><ins>+ default64 = P_DEF64( u->itab_entry->prefix );
</ins><span class="cx"> /* calculate effective operand size */
</span><del>- if ( REX_W( u->pfx_rex ) ) {
</del><ins>+ if (REX_W(u->_rex)) {
</ins><span class="cx"> u->opr_mode = 64;
</span><span class="cx"> } else if ( u->pfx_opr ) {
</span><span class="cx"> u->opr_mode = 16;
</span><span class="lines">@@ -897,7 +1016,7 @@
</span><span class="cx"> * the effective operand size in the absence of rex.w
</span><span class="cx"> * prefix is 32.
</span><span class="cx"> */
</span><del>- u->opr_mode = ( u->default64 ) ? 64 : 32;
</del><ins>+ u->opr_mode = default64 ? 64 : 32;
</ins><span class="cx"> }
</span><span class="cx">
</span><span class="cx"> /* calculate effective address size */
</span><span class="lines">@@ -910,45 +1029,18 @@
</span><span class="cx"> u->adr_mode = ( u->pfx_adr ) ? 32 : 16;
</span><span class="cx"> }
</span><span class="cx">
</span><del>- /* These flags determine which operand to apply the operand size
- * cast to.
- */
- u->c1 = ( P_C1( u->itab_entry->prefix ) ) ? 1 : 0;
- u->c2 = ( P_C2( u->itab_entry->prefix ) ) ? 1 : 0;
- u->c3 = ( P_C3( u->itab_entry->prefix ) ) ? 1 : 0;
-
- /* set flags for implicit addressing */
- u->implicit_addr = P_IMPADDR( u->itab_entry->prefix );
-
</del><span class="cx"> return 0;
</span><span class="cx"> }
</span><span class="cx">
</span><del>-static int gen_hex( struct ud *u )
-{
- unsigned int i;
- unsigned char *src_ptr = ud_inp_sess( u );
- char* src_hex;
</del><span class="cx">
</span><del>- /* bail out if in error stat. */
- if ( u->error ) return -1;
- /* output buffer pointe */
- src_hex = ( char* ) u->insn_hexcode;
- /* for each byte used to decode instruction */
- for ( i = 0; i < u->inp_ctr; ++i, ++src_ptr) {
- sprintf( src_hex, "%02x", *src_ptr & 0xFF );
- src_hex += 2;
- }
- return 0;
-}
-
-
-static inline int
</del><ins>+static UD_INLINE int
</ins><span class="cx"> decode_insn(struct ud *u, uint16_t ptr)
</span><span class="cx"> {
</span><del>- ASSERT((ptr & 0x8000) == 0);
</del><ins>+ UD_ASSERT((ptr & 0x8000) == 0);
</ins><span class="cx"> u->itab_entry = &ud_itab[ ptr ];
</span><span class="cx"> u->mnemonic = u->itab_entry->mnemonic;
</span><del>- return (resolve_mode(u) == 0 &&
</del><ins>+ return (resolve_pfx_str(u) == 0 &&
+ resolve_mode(u) == 0 &&
</ins><span class="cx"> decode_operands(u) == 0 &&
</span><span class="cx"> resolve_mnemonic(u) == 0) ? 0 : -1;
</span><span class="cx"> }
</span><span class="lines">@@ -965,19 +1057,19 @@
</span><span class="cx"> * valid entry in the table, decode the operands, and read the final
</span><span class="cx"> * byte to resolve the menmonic.
</span><span class="cx"> */
</span><del>-static inline int
</del><ins>+static UD_INLINE int
</ins><span class="cx"> decode_3dnow(struct ud* u)
</span><span class="cx"> {
</span><span class="cx"> uint16_t ptr;
</span><del>- ASSERT(u->le->type == UD_TAB__OPC_3DNOW);
- ASSERT(u->le->table[0xc] != 0);
</del><ins>+ UD_ASSERT(u->le->type == UD_TAB__OPC_3DNOW);
+ UD_ASSERT(u->le->table[0xc] != 0);
</ins><span class="cx"> decode_insn(u, u->le->table[0xc]);
</span><del>- ud_inp_next(u);
</del><ins>+ inp_next(u);
</ins><span class="cx"> if (u->error) {
</span><span class="cx"> return -1;
</span><span class="cx"> }
</span><del>- ptr = u->le->table[ud_inp_curr(u)];
- ASSERT((ptr & 0x8000) == 0);
</del><ins>+ ptr = u->le->table[inp_curr(u)];
+ UD_ASSERT((ptr & 0x8000) == 0);
</ins><span class="cx"> u->mnemonic = ud_itab[ptr].mnemonic;
</span><span class="cx"> return 0;
</span><span class="cx"> }
</span><span class="lines">@@ -986,7 +1078,18 @@
</span><span class="cx"> static int
</span><span class="cx"> decode_ssepfx(struct ud *u)
</span><span class="cx"> {
</span><del>- uint8_t idx = ((u->pfx_insn & 0xf) + 1) / 2;
</del><ins>+ uint8_t idx;
+ uint8_t pfx;
+
+ /*
+ * String prefixes (f2, f3) take precedence over operand
+ * size prefix (66).
+ */
+ pfx = u->pfx_str;
+ if (pfx == 0) {
+ pfx = u->pfx_opr;
+ }
+ idx = ((pfx & 0xf) + 1) / 2;
</ins><span class="cx"> if (u->le->table[idx] == 0) {
</span><span class="cx"> idx = 0;
</span><span class="cx"> }
</span><span class="lines">@@ -995,23 +1098,50 @@
</span><span class="cx"> * "Consume" the prefix as a part of the opcode, so it is no
</span><span class="cx"> * longer exported as an instruction prefix.
</span><span class="cx"> */
</span><del>- switch (u->pfx_insn) {
- case 0xf2:
- u->pfx_repne = 0;
- break;
- case 0xf3:
- u->pfx_rep = 0;
- u->pfx_repe = 0;
- break;
- case 0x66:
</del><ins>+ u->pfx_str = 0;
+ if (pfx == 0x66) {
+ /*
+ * consume "66" only if it was used for decoding, leaving
+ * it to be used as an operands size override for some
+ * simd instructions.
+ */
</ins><span class="cx"> u->pfx_opr = 0;
</span><del>- break;
</del><span class="cx"> }
</span><span class="cx"> }
</span><span class="cx"> return decode_ext(u, u->le->table[idx]);
</span><span class="cx"> }
</span><span class="cx">
</span><span class="cx">
</span><ins>+static int
+decode_vex(struct ud *u)
+{
+ uint8_t index;
+ if (u->dis_mode != 64 && MODRM_MOD(inp_peek(u)) != 0x3) {
+ index = 0;
+ } else {
+ u->vex_op = inp_curr(u);
+ u->vex_b1 = inp_next(u);
+ if (u->vex_op == 0xc4) {
+ uint8_t pp, m;
+ /* 3-byte vex */
+ u->vex_b2 = inp_next(u);
+ UD_RETURN_ON_ERROR(u);
+ m = u->vex_b1 & 0x1f;
+ if (m == 0 || m > 3) {
+ UD_RETURN_WITH_ERROR(u, "reserved vex.m-mmmm value");
+ }
+ pp = u->vex_b2 & 0x3;
+ index = (pp << 2) | m;
+ } else {
+ /* 2-byte vex */
+ UD_ASSERT(u->vex_op == 0xc5);
+ index = 0x1 | ((u->vex_b1 & 0x3) << 2);
+ }
+ }
+ return decode_ext(u, u->le->table[index]);
+}
+
+
</ins><span class="cx"> /*
</span><span class="cx"> * decode_ext()
</span><span class="cx"> *
</span><span class="lines">@@ -1038,7 +1168,7 @@
</span><span class="cx"> * 16 = 0,, 32 = 1, 64 = 2
</span><span class="cx"> */
</span><span class="cx"> case UD_TAB__OPC_MODE:
</span><del>- idx = u->dis_mode / 32;
</del><ins>+ idx = u->dis_mode != 64 ? 0 : 1;
</ins><span class="cx"> break;
</span><span class="cx"> case UD_TAB__OPC_OSIZE:
</span><span class="cx"> idx = eff_opr_mode(u->dis_mode, REX_W(u->pfx_rex), u->pfx_opr) / 32;
</span><span class="lines">@@ -1067,8 +1197,19 @@
</span><span class="cx"> break;
</span><span class="cx"> case UD_TAB__OPC_SSE:
</span><span class="cx"> return decode_ssepfx(u);
</span><ins>+ case UD_TAB__OPC_VEX:
+ return decode_vex(u);
+ case UD_TAB__OPC_VEX_W:
+ idx = vex_w(u);
+ break;
+ case UD_TAB__OPC_VEX_L:
+ idx = vex_l(u);
+ break;
+ case UD_TAB__OPC_TABLE:
+ inp_next(u);
+ return decode_opcode(u);
</ins><span class="cx"> default:
</span><del>- ASSERT(!"not reached");
</del><ins>+ UD_ASSERT(!"not reached");
</ins><span class="cx"> break;
</span><span class="cx"> }
</span><span class="cx">
</span><span class="lines">@@ -1076,22 +1217,13 @@
</span><span class="cx"> }
</span><span class="cx">
</span><span class="cx">
</span><del>-static inline int
</del><ins>+static int
</ins><span class="cx"> decode_opcode(struct ud *u)
</span><span class="cx"> {
</span><span class="cx"> uint16_t ptr;
</span><del>- ASSERT(u->le->type == UD_TAB__OPC_TABLE);
- ud_inp_next(u);
- if (u->error) {
- return -1;
- }
- ptr = u->le->table[ud_inp_curr(u)];
- if (ptr & 0x8000) {
- u->le = &ud_lookup_table_list[ptr & ~0x8000];
- if (u->le->type == UD_TAB__OPC_TABLE) {
- return decode_opcode(u);
- }
- }
</del><ins>+ UD_ASSERT(u->le->type == UD_TAB__OPC_TABLE);
+ UD_RETURN_ON_ERROR(u);
+ ptr = u->le->table[inp_curr(u)];
</ins><span class="cx"> return decode_ext(u, ptr);
</span><span class="cx"> }
</span><span class="cx">
</span><span class="lines">@@ -1103,7 +1235,7 @@
</span><span class="cx"> unsigned int
</span><span class="cx"> ud_decode(struct ud *u)
</span><span class="cx"> {
</span><del>- ud_inp_start(u);
</del><ins>+ inp_start(u);
</ins><span class="cx"> clear_insn(u);
</span><span class="cx"> u->le = &ud_lookup_table_list[0];
</span><span class="cx"> u->error = decode_prefixes(u) == -1 ||
</span><span class="lines">@@ -1114,7 +1246,7 @@
</span><span class="cx"> /* clear out the decode data. */
</span><span class="cx"> clear_insn(u);
</span><span class="cx"> /* mark the sequence of bytes as invalid. */
</span><del>- u->itab_entry = & s_ie__invalid;
</del><ins>+ u->itab_entry = &ud_itab[0]; /* entry 0 is invalid */
</ins><span class="cx"> u->mnemonic = u->itab_entry->mnemonic;
</span><span class="cx"> }
</span><span class="cx">
</span><span class="lines">@@ -1127,16 +1259,15 @@
</span><span class="cx"> u->pfx_seg = 0;
</span><span class="cx">
</span><span class="cx"> u->insn_offset = u->pc; /* set offset of instruction */
</span><del>- u->insn_fill = 0; /* set translation buffer index to 0 */
</del><ins>+ u->asm_buf_fill = 0; /* set translation buffer index to 0 */
</ins><span class="cx"> u->pc += u->inp_ctr; /* move program counter by bytes decoded */
</span><del>- gen_hex( u ); /* generate hex code */
</del><span class="cx">
</span><span class="cx"> /* return number of bytes disassembled. */
</span><span class="cx"> return u->inp_ctr;
</span><span class="cx"> }
</span><span class="cx">
</span><ins>+#endif // USE(UDIS86)
+
</ins><span class="cx"> /*
</span><span class="cx"> vim: set ts=2 sw=2 expandtab
</span><span class="cx"> */
</span><del>-
-#endif // USE(UDIS86)
</del></span></pre></div>
<a id="trunkSourceJavaScriptCoredisassemblerudis86udis86_decodeh"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/disassembler/udis86/udis86_decode.h (198831 => 198832)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/disassembler/udis86/udis86_decode.h 2016-03-30 07:14:10 UTC (rev 198831)
+++ trunk/Source/JavaScriptCore/disassembler/udis86/udis86_decode.h 2016-03-30 07:17:14 UTC (rev 198832)
</span><span class="lines">@@ -27,74 +27,45 @@
</span><span class="cx"> #define UD_DECODE_H
</span><span class="cx">
</span><span class="cx"> #include "udis86_types.h"
</span><ins>+#include "udis86_udint.h"
</ins><span class="cx"> #include "udis86_itab.h"
</span><span class="cx">
</span><span class="cx"> #define MAX_INSN_LENGTH 15
</span><span class="cx">
</span><del>-/* register classes */
-#define T_NONE 0
-#define T_GPR 1
-#define T_MMX 2
-#define T_CRG 3
-#define T_DBG 4
-#define T_SEG 5
-#define T_XMM 6
-
</del><span class="cx"> /* itab prefix bits */
</span><span class="cx"> #define P_none ( 0 )
</span><del>-#define P_cast ( 1 << 0 )
-#define P_CAST(n) ( ( n >> 0 ) & 1 )
-#define P_c1 ( 1 << 0 )
-#define P_C1(n) ( ( n >> 0 ) & 1 )
-#define P_rexb ( 1 << 1 )
-#define P_REXB(n) ( ( n >> 1 ) & 1 )
-#define P_depM ( 1 << 2 )
-#define P_DEPM(n) ( ( n >> 2 ) & 1 )
-#define P_c3 ( 1 << 3 )
-#define P_C3(n) ( ( n >> 3 ) & 1 )
-#define P_inv64 ( 1 << 4 )
-#define P_INV64(n) ( ( n >> 4 ) & 1 )
</del><ins>+
+#define P_inv64 ( 1 << 0 )
+#define P_INV64(n) ( ( n >> 0 ) & 1 )
+#define P_def64 ( 1 << 1 )
+#define P_DEF64(n) ( ( n >> 1 ) & 1 )
+
+#define P_oso ( 1 << 2 )
+#define P_OSO(n) ( ( n >> 2 ) & 1 )
+#define P_aso ( 1 << 3 )
+#define P_ASO(n) ( ( n >> 3 ) & 1 )
+
+#define P_rexb ( 1 << 4 )
+#define P_REXB(n) ( ( n >> 4 ) & 1 )
</ins><span class="cx"> #define P_rexw ( 1 << 5 )
</span><span class="cx"> #define P_REXW(n) ( ( n >> 5 ) & 1 )
</span><del>-#define P_c2 ( 1 << 6 )
-#define P_C2(n) ( ( n >> 6 ) & 1 )
-#define P_def64 ( 1 << 7 )
-#define P_DEF64(n) ( ( n >> 7 ) & 1 )
-#define P_rexr ( 1 << 8 )
-#define P_REXR(n) ( ( n >> 8 ) & 1 )
-#define P_oso ( 1 << 9 )
-#define P_OSO(n) ( ( n >> 9 ) & 1 )
-#define P_aso ( 1 << 10 )
-#define P_ASO(n) ( ( n >> 10 ) & 1 )
-#define P_rexx ( 1 << 11 )
-#define P_REXX(n) ( ( n >> 11 ) & 1 )
-#define P_ImpAddr ( 1 << 12 )
-#define P_IMPADDR(n) ( ( n >> 12 ) & 1 )
-#define P_seg ( 1 << 13 )
-#define P_SEG(n) ( ( n >> 13 ) & 1 )
-#define P_sext ( 1 << 14 )
-#define P_SEXT(n) ( ( n >> 14 ) & 1 )
</del><ins>+#define P_rexr ( 1 << 6 )
+#define P_REXR(n) ( ( n >> 6 ) & 1 )
+#define P_rexx ( 1 << 7 )
+#define P_REXX(n) ( ( n >> 7 ) & 1 )
</ins><span class="cx">
</span><del>-/* rex prefix bits */
-#define REX_W(r) ( ( 0xF & ( r ) ) >> 3 )
-#define REX_R(r) ( ( 0x7 & ( r ) ) >> 2 )
-#define REX_X(r) ( ( 0x3 & ( r ) ) >> 1 )
-#define REX_B(r) ( ( 0x1 & ( r ) ) >> 0 )
-#define REX_PFX_MASK(n) ( ( P_REXW(n) << 3 ) | \
- ( P_REXR(n) << 2 ) | \
- ( P_REXX(n) << 1 ) | \
- ( P_REXB(n) << 0 ) )
</del><ins>+#define P_seg ( 1 << 8 )
+#define P_SEG(n) ( ( n >> 8 ) & 1 )
</ins><span class="cx">
</span><del>-/* scable-index-base bits */
-#define SIB_S(b) ( ( b ) >> 6 )
-#define SIB_I(b) ( ( ( b ) >> 3 ) & 7 )
-#define SIB_B(b) ( ( b ) & 7 )
</del><ins>+#define P_vexl ( 1 << 9 )
+#define P_VEXL(n) ( ( n >> 9 ) & 1 )
+#define P_vexw ( 1 << 10 )
+#define P_VEXW(n) ( ( n >> 10 ) & 1 )
</ins><span class="cx">
</span><del>-/* modrm bits */
-#define MODRM_REG(b) ( ( ( b ) >> 3 ) & 7 )
-#define MODRM_NNN(b) ( ( ( b ) >> 3 ) & 7 )
-#define MODRM_MOD(b) ( ( ( b ) >> 6 ) & 3 )
-#define MODRM_RM(b) ( ( b ) & 7 )
</del><ins>+#define P_str ( 1 << 11 )
+#define P_STR(n) ( ( n >> 11 ) & 1 )
+#define P_strz ( 1 << 12 )
+#define P_STR_ZF(n) ( ( n >> 12 ) & 1 )
</ins><span class="cx">
</span><span class="cx"> /* operand type constants -- order is important! */
</span><span class="cx">
</span><span class="lines">@@ -102,26 +73,16 @@
</span><span class="cx"> OP_NONE,
</span><span class="cx">
</span><span class="cx"> OP_A, OP_E, OP_M, OP_G,
</span><del>- OP_I,
</del><ins>+ OP_I, OP_F,
</ins><span class="cx">
</span><del>- OP_AL, OP_CL, OP_DL, OP_BL,
- OP_AH, OP_CH, OP_DH, OP_BH,
</del><ins>+ OP_R0, OP_R1, OP_R2, OP_R3,
+ OP_R4, OP_R5, OP_R6, OP_R7,
</ins><span class="cx">
</span><del>- OP_ALr8b, OP_CLr9b, OP_DLr10b, OP_BLr11b,
- OP_AHr12b, OP_CHr13b, OP_DHr14b, OP_BHr15b,
</del><ins>+ OP_AL, OP_CL, OP_DL,
+ OP_AX, OP_CX, OP_DX,
+ OP_eAX, OP_eCX, OP_eDX,
+ OP_rAX, OP_rCX, OP_rDX,
</ins><span class="cx">
</span><del>- OP_AX, OP_CX, OP_DX, OP_BX,
- OP_SI, OP_DI, OP_SP, OP_BP,
-
- OP_rAX, OP_rCX, OP_rDX, OP_rBX,
- OP_rSP, OP_rBP, OP_rSI, OP_rDI,
-
- OP_rAXr8, OP_rCXr9, OP_rDXr10, OP_rBXr11,
- OP_rSPr12, OP_rBPr13, OP_rSIr14, OP_rDIr15,
-
- OP_eAX, OP_eCX, OP_eDX, OP_eBX,
- OP_eSP, OP_eBP, OP_eSI, OP_eDI,
-
</del><span class="cx"> OP_ES, OP_CS, OP_SS, OP_DS,
</span><span class="cx"> OP_FS, OP_GS,
</span><span class="cx">
</span><span class="lines">@@ -129,45 +90,71 @@
</span><span class="cx"> OP_ST4, OP_ST5, OP_ST6, OP_ST7,
</span><span class="cx">
</span><span class="cx"> OP_J, OP_S, OP_O,
</span><del>- OP_I1, OP_I3,
</del><ins>+ OP_I1, OP_I3, OP_sI,
</ins><span class="cx">
</span><span class="cx"> OP_V, OP_W, OP_Q, OP_P,
</span><ins>+ OP_U, OP_N, OP_MU, OP_H,
+ OP_L,
</ins><span class="cx">
</span><del>- OP_R, OP_C, OP_D, OP_VR, OP_PR,
</del><ins>+ OP_R, OP_C, OP_D,
</ins><span class="cx">
</span><span class="cx"> OP_MR
</span><span class="cx"> } UD_ATTR_PACKED;
</span><span class="cx">
</span><span class="cx">
</span><del>-/* operand size constants */
</del><ins>+/*
+ * Operand size constants
+ *
+ * Symbolic constants for various operand sizes. Some of these constants
+ * are given a value equal to the width of the data (SZ_B == 8), such
+ * that they maybe used interchangeably in the internals. Modifying them
+ * will most certainly break things!
+ */
+typedef uint16_t ud_operand_size_t;
</ins><span class="cx">
</span><del>-enum ud_operand_size {
- SZ_NA = 0,
- SZ_Z = 1,
- SZ_V = 2,
- SZ_P = 3,
- SZ_WP = 4,
- SZ_DP = 5,
- SZ_MDQ = 6,
- SZ_RDQ = 7,
</del><ins>+#define SZ_NA 0
+#define SZ_Z 1
+#define SZ_V 2
+#define SZ_Y 3
+#define SZ_X 4
+#define SZ_RDQ 7
+#define SZ_B 8
+#define SZ_W 16
+#define SZ_D 32
+#define SZ_Q 64
+#define SZ_T 80
+#define SZ_O 12
+#define SZ_DQ 128 /* double quad */
+#define SZ_QQ 256 /* quad quad */
</ins><span class="cx">
</span><del>- /* the following values are used as is,
- * and thus hard-coded. changing them
- * will break internals
- */
- SZ_B = 8,
- SZ_W = 16,
- SZ_D = 32,
- SZ_Q = 64,
- SZ_T = 80,
- SZ_O = 128,
</del><ins>+/*
+ * Complex size types; that encode sizes for operands of type MR (memory or
+ * register); for internal use only. Id space above 256.
+ */
+#define SZ_BD ((SZ_B << 8) | SZ_D)
+#define SZ_BV ((SZ_B << 8) | SZ_V)
+#define SZ_WD ((SZ_W << 8) | SZ_D)
+#define SZ_WV ((SZ_W << 8) | SZ_V)
+#define SZ_WY ((SZ_W << 8) | SZ_Y)
+#define SZ_DY ((SZ_D << 8) | SZ_Y)
+#define SZ_WO ((SZ_W << 8) | SZ_O)
+#define SZ_DO ((SZ_D << 8) | SZ_O)
+#define SZ_QO ((SZ_Q << 8) | SZ_O)
</ins><span class="cx">
</span><del>- SZ_WV = 17,
- SZ_BV = 18,
- SZ_DY = 19
</del><span class="cx">
</span><del>-} UD_ATTR_PACKED;
</del><ins>+/* resolve complex size type.
+ */
+static UD_INLINE ud_operand_size_t
+Mx_mem_size(ud_operand_size_t size)
+{
+ return (size >> 8) & 0xff;
+}
</ins><span class="cx">
</span><ins>+static UD_INLINE ud_operand_size_t
+Mx_reg_size(ud_operand_size_t size)
+{
+ return size & 0xff;
+}
</ins><span class="cx">
</span><span class="cx"> /* A single operand of an entry in the instruction table.
</span><span class="cx"> * (internal use only)
</span><span class="lines">@@ -175,7 +162,7 @@
</span><span class="cx"> struct ud_itab_entry_operand
</span><span class="cx"> {
</span><span class="cx"> enum ud_operand_code type;
</span><del>- enum ud_operand_size size;
</del><ins>+ ud_operand_size_t size;
</ins><span class="cx"> };
</span><span class="cx">
</span><span class="cx">
</span><span class="lines">@@ -188,6 +175,7 @@
</span><span class="cx"> struct ud_itab_entry_operand operand1;
</span><span class="cx"> struct ud_itab_entry_operand operand2;
</span><span class="cx"> struct ud_itab_entry_operand operand3;
</span><ins>+ struct ud_itab_entry_operand operand4;
</ins><span class="cx"> uint32_t prefix;
</span><span class="cx"> };
</span><span class="cx">
</span><span class="lines">@@ -197,55 +185,6 @@
</span><span class="cx"> const char *meta;
</span><span class="cx"> };
</span><span class="cx">
</span><del>-
-static inline unsigned int sse_pfx_idx( const unsigned int pfx )
-{
- /* 00 = 0
- * f2 = 1
- * f3 = 2
- * 66 = 3
- */
- return ( ( pfx & 0xf ) + 1 ) / 2;
-}
-
-static inline unsigned int mode_idx( const unsigned int mode )
-{
- /* 16 = 0
- * 32 = 1
- * 64 = 2
- */
- return ( mode / 32 );
-}
-
-static inline unsigned int modrm_mod_idx( const unsigned int mod )
-{
- /* !11 = 0
- * 11 = 1
- */
- return ( mod + 1 ) / 4;
-}
-
-static inline unsigned int vendor_idx( const unsigned int vendor )
-{
- switch ( vendor ) {
- case UD_VENDOR_AMD: return 0;
- case UD_VENDOR_INTEL: return 1;
- case UD_VENDOR_ANY: return 2;
- default: return 2;
- }
-}
-
-static inline unsigned int is_group_ptr( uint16_t ptr )
-{
- return ( 0x8000 & ptr );
-}
-
-static inline unsigned int group_idx( uint16_t ptr )
-{
- return ( ~0x8000 & ptr );
-}
-
-
</del><span class="cx"> extern struct ud_itab_entry ud_itab[];
</span><span class="cx"> extern struct ud_lookup_table_list_entry ud_lookup_table_list[];
</span><span class="cx">
</span></span></pre></div>
<a id="trunkSourceJavaScriptCoredisassemblerudis86udis86_externh"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/disassembler/udis86/udis86_extern.h (198831 => 198832)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/disassembler/udis86/udis86_extern.h 2016-03-30 07:14:10 UTC (rev 198831)
+++ trunk/Source/JavaScriptCore/disassembler/udis86/udis86_extern.h 2016-03-30 07:17:14 UTC (rev 198832)
</span><span class="lines">@@ -1,6 +1,6 @@
</span><span class="cx"> /* udis86 - libudis86/extern.h
</span><span class="cx"> *
</span><del>- * Copyright (c) 2002-2009 Vivek Thampi
</del><ins>+ * Copyright (c) 2002-2009, 2013 Vivek Thampi
</ins><span class="cx"> * All rights reserved.
</span><span class="cx"> *
</span><span class="cx"> * Redistribution and use in source and binary forms, with or without modification,
</span><span class="lines">@@ -32,57 +32,82 @@
</span><span class="cx">
</span><span class="cx"> #include "udis86_types.h"
</span><span class="cx">
</span><ins>+#if defined(_MSC_VER) && defined(_USRDLL)
+# ifdef LIBUDIS86_EXPORTS
+# define LIBUDIS86_DLLEXTERN __declspec(dllexport)
+# else
+# define LIBUDIS86_DLLEXTERN __declspec(dllimport)
+# endif
+#else
+# define LIBUDIS86_DLLEXTERN
+#endif
+
</ins><span class="cx"> /* ============================= PUBLIC API ================================= */
</span><span class="cx">
</span><del>-extern void ud_init(struct ud*);
</del><ins>+extern LIBUDIS86_DLLEXTERN void ud_init(struct ud*);
</ins><span class="cx">
</span><del>-extern void ud_set_mode(struct ud*, uint8_t);
</del><ins>+extern LIBUDIS86_DLLEXTERN void ud_set_mode(struct ud*, uint8_t);
</ins><span class="cx">
</span><del>-extern void ud_set_pc(struct ud*, uint64_t);
</del><ins>+extern LIBUDIS86_DLLEXTERN void ud_set_pc(struct ud*, uint64_t);
</ins><span class="cx">
</span><del>-extern void ud_set_input_hook(struct ud*, int (*)(struct ud*));
</del><ins>+extern LIBUDIS86_DLLEXTERN void ud_set_input_hook(struct ud*, int (*)(struct ud*));
</ins><span class="cx">
</span><del>-extern void ud_set_input_buffer(struct ud*, uint8_t*, size_t);
</del><ins>+extern LIBUDIS86_DLLEXTERN void ud_set_input_buffer(struct ud*, const uint8_t*, size_t);
</ins><span class="cx">
</span><span class="cx"> #ifndef __UD_STANDALONE__
</span><del>-extern void ud_set_input_file(struct ud*, FILE*);
</del><ins>+extern LIBUDIS86_DLLEXTERN void ud_set_input_file(struct ud*, FILE*);
</ins><span class="cx"> #endif /* __UD_STANDALONE__ */
</span><span class="cx">
</span><del>-extern void ud_set_vendor(struct ud*, unsigned);
</del><ins>+extern LIBUDIS86_DLLEXTERN void ud_set_vendor(struct ud*, unsigned);
</ins><span class="cx">
</span><del>-extern void ud_set_syntax(struct ud*, void (*)(struct ud*));
</del><ins>+extern LIBUDIS86_DLLEXTERN void ud_set_syntax(struct ud*, void (*)(struct ud*));
</ins><span class="cx">
</span><del>-extern void ud_input_skip(struct ud*, size_t);
</del><ins>+extern LIBUDIS86_DLLEXTERN void ud_input_skip(struct ud*, size_t);
</ins><span class="cx">
</span><del>-extern int ud_input_end(struct ud*);
</del><ins>+extern LIBUDIS86_DLLEXTERN int ud_input_end(const struct ud*);
</ins><span class="cx">
</span><del>-extern unsigned int ud_decode(struct ud*);
</del><ins>+extern LIBUDIS86_DLLEXTERN unsigned int ud_decode(struct ud*);
</ins><span class="cx">
</span><del>-extern unsigned int ud_disassemble(struct ud*);
</del><ins>+extern LIBUDIS86_DLLEXTERN unsigned int ud_disassemble(struct ud*);
</ins><span class="cx">
</span><del>-extern void ud_translate_intel(struct ud*);
</del><ins>+extern LIBUDIS86_DLLEXTERN void ud_translate_intel(struct ud*);
</ins><span class="cx">
</span><del>-extern void ud_translate_att(struct ud*);
</del><ins>+extern LIBUDIS86_DLLEXTERN void ud_translate_att(struct ud*);
</ins><span class="cx">
</span><del>-extern char* ud_insn_asm(struct ud* u);
</del><ins>+extern LIBUDIS86_DLLEXTERN const char* ud_insn_asm(const struct ud* u);
</ins><span class="cx">
</span><del>-extern uint8_t* ud_insn_ptr(struct ud* u);
</del><ins>+extern LIBUDIS86_DLLEXTERN const uint8_t* ud_insn_ptr(const struct ud* u);
</ins><span class="cx">
</span><del>-extern uint64_t ud_insn_off(struct ud*);
</del><ins>+extern LIBUDIS86_DLLEXTERN uint64_t ud_insn_off(const struct ud*);
</ins><span class="cx">
</span><del>-extern char* ud_insn_hex(struct ud*);
</del><ins>+extern LIBUDIS86_DLLEXTERN const char* ud_insn_hex(struct ud*);
</ins><span class="cx">
</span><del>-extern unsigned int ud_insn_len(struct ud* u);
</del><ins>+extern LIBUDIS86_DLLEXTERN unsigned int ud_insn_len(const struct ud* u);
</ins><span class="cx">
</span><del>-extern const char* ud_lookup_mnemonic(enum ud_mnemonic_code c);
</del><ins>+extern LIBUDIS86_DLLEXTERN const struct ud_operand* ud_insn_opr(const struct ud *u, unsigned int n);
</ins><span class="cx">
</span><del>-extern void ud_set_user_opaque_data(struct ud*, void*);
</del><ins>+extern LIBUDIS86_DLLEXTERN int ud_opr_is_sreg(const struct ud_operand *opr);
</ins><span class="cx">
</span><del>-extern void *ud_get_user_opaque_data(struct ud*);
</del><ins>+extern LIBUDIS86_DLLEXTERN int ud_opr_is_gpr(const struct ud_operand *opr);
</ins><span class="cx">
</span><ins>+extern LIBUDIS86_DLLEXTERN enum ud_mnemonic_code ud_insn_mnemonic(const struct ud *u);
+
+extern LIBUDIS86_DLLEXTERN const char* ud_lookup_mnemonic(enum ud_mnemonic_code c);
+
+extern LIBUDIS86_DLLEXTERN void ud_set_user_opaque_data(struct ud*, void*);
+
+extern LIBUDIS86_DLLEXTERN void* ud_get_user_opaque_data(const struct ud*);
+
+extern LIBUDIS86_DLLEXTERN void ud_set_asm_buffer(struct ud *u, char *buf, size_t size);
+
+extern LIBUDIS86_DLLEXTERN void ud_set_sym_resolver(struct ud *u,
+ const char* (*resolver)(struct ud*,
+ uint64_t addr,
+ int64_t *offset));
+
</ins><span class="cx"> /* ========================================================================== */
</span><span class="cx">
</span><span class="cx"> #ifdef __cplusplus
</span><span class="cx"> }
</span><span class="cx"> #endif
</span><del>-#endif
</del><ins>+#endif /* UD_EXTERN_H */
</ins></span></pre></div>
<a id="trunkSourceJavaScriptCoredisassemblerudis86udis86_inputc"></a>
<div class="delfile"><h4>Deleted: trunk/Source/JavaScriptCore/disassembler/udis86/udis86_input.c (198831 => 198832)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/disassembler/udis86/udis86_input.c 2016-03-30 07:14:10 UTC (rev 198831)
+++ trunk/Source/JavaScriptCore/disassembler/udis86/udis86_input.c 2016-03-30 07:17:14 UTC (rev 198832)
</span><span class="lines">@@ -1,262 +0,0 @@
</span><del>-/* udis86 - libudis86/input.c
- *
- * Copyright (c) 2002-2009 Vivek Thampi
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "config.h"
-
-#if USE(UDIS86)
-
-#include "udis86_extern.h"
-#include "udis86_types.h"
-#include "udis86_input.h"
-
-/* -----------------------------------------------------------------------------
- * inp_buff_hook() - Hook for buffered inputs.
- * -----------------------------------------------------------------------------
- */
-static int
-inp_buff_hook(struct ud* u)
-{
- if (u->inp_buff < u->inp_buff_end)
- return *u->inp_buff++;
- else return -1;
-}
-
-#ifndef __UD_STANDALONE__
-/* -----------------------------------------------------------------------------
- * inp_file_hook() - Hook for FILE inputs.
- * -----------------------------------------------------------------------------
- */
-static int
-inp_file_hook(struct ud* u)
-{
- return fgetc(u->inp_file);
-}
-#endif /* __UD_STANDALONE__*/
-
-/* =============================================================================
- * ud_inp_set_hook() - Sets input hook.
- * =============================================================================
- */
-extern void
-ud_set_input_hook(register struct ud* u, int (*hook)(struct ud*))
-{
- u->inp_hook = hook;
- ud_inp_init(u);
-}
-
-extern void
-ud_set_user_opaque_data( struct ud * u, void * opaque )
-{
- u->user_opaque_data = opaque;
-}
-
-extern void *
-ud_get_user_opaque_data( struct ud * u )
-{
- return u->user_opaque_data;
-}
-
-/* =============================================================================
- * ud_inp_set_buffer() - Set buffer as input.
- * =============================================================================
- */
-extern void
-ud_set_input_buffer(register struct ud* u, uint8_t* buf, size_t len)
-{
- u->inp_hook = inp_buff_hook;
- u->inp_buff = buf;
- u->inp_buff_end = buf + len;
- ud_inp_init(u);
-}
-
-#ifndef __UD_STANDALONE__
-/* =============================================================================
- * ud_input_set_file() - Set buffer as input.
- * =============================================================================
- */
-extern void
-ud_set_input_file(register struct ud* u, FILE* f)
-{
- u->inp_hook = inp_file_hook;
- u->inp_file = f;
- ud_inp_init(u);
-}
-#endif /* __UD_STANDALONE__ */
-
-/* =============================================================================
- * ud_input_skip() - Skip n input bytes.
- * =============================================================================
- */
-extern void
-ud_input_skip(struct ud* u, size_t n)
-{
- while (n--) {
- u->inp_hook(u);
- }
-}
-
-/* =============================================================================
- * ud_input_end() - Test for end of input.
- * =============================================================================
- */
-extern int
-ud_input_end(struct ud* u)
-{
- return (u->inp_curr == u->inp_fill) && u->inp_end;
-}
-
-/* -----------------------------------------------------------------------------
- * ud_inp_next() - Loads and returns the next byte from input.
- *
- * inp_curr and inp_fill are pointers to the cache. The program is written based
- * on the property that they are 8-bits in size, and will eventually wrap around
- * forming a circular buffer. So, the size of the cache is 256 in size, kind of
- * unnecessary yet optimized.
- *
- * A buffer inp_sess stores the bytes disassembled for a single session.
- * -----------------------------------------------------------------------------
- */
-extern uint8_t ud_inp_next(struct ud* u)
-{
- int c = -1;
- /* if current pointer is not upto the fill point in the
- * input cache.
- */
- if ( u->inp_curr != u->inp_fill ) {
- c = u->inp_cache[ ++u->inp_curr ];
- /* if !end-of-input, call the input hook and get a byte */
- } else if ( u->inp_end || ( c = u->inp_hook( u ) ) == -1 ) {
- /* end-of-input, mark it as an error, since the decoder,
- * expected a byte more.
- */
- u->error = 1;
- /* flag end of input */
- u->inp_end = 1;
- return 0;
- } else {
- /* increment pointers, we have a new byte. */
- u->inp_curr = ++u->inp_fill;
- /* add the byte to the cache */
- u->inp_cache[ u->inp_fill ] = c;
- }
- /* record bytes input per decode-session. */
- u->inp_sess[ u->inp_ctr++ ] = c;
- /* return byte */
- return ( uint8_t ) c;
-}
-
-/* -----------------------------------------------------------------------------
- * ud_inp_back() - Move back a single byte in the stream.
- * -----------------------------------------------------------------------------
- */
-extern void
-ud_inp_back(struct ud* u)
-{
- if ( u->inp_ctr > 0 ) {
- --u->inp_curr;
- --u->inp_ctr;
- }
-}
-
-/* -----------------------------------------------------------------------------
- * ud_inp_peek() - Peek into the next byte in source.
- * -----------------------------------------------------------------------------
- */
-extern uint8_t
-ud_inp_peek(struct ud* u)
-{
- uint8_t r = ud_inp_next(u);
- if ( !u->error ) ud_inp_back(u); /* Don't backup if there was an error */
- return r;
-}
-
-/* -----------------------------------------------------------------------------
- * ud_inp_move() - Move ahead n input bytes.
- * -----------------------------------------------------------------------------
- */
-extern void
-ud_inp_move(struct ud* u, size_t n)
-{
- while (n--)
- ud_inp_next(u);
-}
-
-/*------------------------------------------------------------------------------
- * ud_inp_uintN() - return uintN from source.
- *------------------------------------------------------------------------------
- */
-extern uint8_t
-ud_inp_uint8(struct ud* u)
-{
- return ud_inp_next(u);
-}
-
-extern uint16_t
-ud_inp_uint16(struct ud* u)
-{
- uint16_t r, ret;
-
- ret = ud_inp_next(u);
- r = ud_inp_next(u);
- return ret | (r << 8);
-}
-
-extern uint32_t
-ud_inp_uint32(struct ud* u)
-{
- uint32_t r, ret;
-
- ret = ud_inp_next(u);
- r = ud_inp_next(u);
- ret = ret | (r << 8);
- r = ud_inp_next(u);
- ret = ret | (r << 16);
- r = ud_inp_next(u);
- return ret | (r << 24);
-}
-
-extern uint64_t
-ud_inp_uint64(struct ud* u)
-{
- uint64_t r, ret;
-
- ret = ud_inp_next(u);
- r = ud_inp_next(u);
- ret = ret | (r << 8);
- r = ud_inp_next(u);
- ret = ret | (r << 16);
- r = ud_inp_next(u);
- ret = ret | (r << 24);
- r = ud_inp_next(u);
- ret = ret | (r << 32);
- r = ud_inp_next(u);
- ret = ret | (r << 40);
- r = ud_inp_next(u);
- ret = ret | (r << 48);
- r = ud_inp_next(u);
- return ret | (r << 56);
-}
-
-#endif // USE(UDIS86)
</del></span></pre></div>
<a id="trunkSourceJavaScriptCoredisassemblerudis86udis86_inputh"></a>
<div class="delfile"><h4>Deleted: trunk/Source/JavaScriptCore/disassembler/udis86/udis86_input.h (198831 => 198832)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/disassembler/udis86/udis86_input.h 2016-03-30 07:14:10 UTC (rev 198831)
+++ trunk/Source/JavaScriptCore/disassembler/udis86/udis86_input.h 2016-03-30 07:17:14 UTC (rev 198832)
</span><span class="lines">@@ -1,67 +0,0 @@
</span><del>-/* udis86 - libudis86/input.h
- *
- * Copyright (c) 2002-2009 Vivek Thampi
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef UD_INPUT_H
-#define UD_INPUT_H
-
-#include "udis86_types.h"
-
-uint8_t ud_inp_next(struct ud*);
-uint8_t ud_inp_peek(struct ud*);
-uint8_t ud_inp_uint8(struct ud*);
-uint16_t ud_inp_uint16(struct ud*);
-uint32_t ud_inp_uint32(struct ud*);
-uint64_t ud_inp_uint64(struct ud*);
-void ud_inp_move(struct ud*, size_t);
-void ud_inp_back(struct ud*);
-
-/* ud_inp_init() - Initializes the input system. */
-#define ud_inp_init(u) \
-do { \
- u->inp_curr = 0; \
- u->inp_fill = 0; \
- u->inp_ctr = 0; \
- u->inp_end = 0; \
-} while (0)
-
-/* ud_inp_start() - Should be called before each de-code operation. */
-#define ud_inp_start(u) u->inp_ctr = 0
-
-/* ud_inp_back() - Resets the current pointer to its position before the current
- * instruction disassembly was started.
- */
-#define ud_inp_reset(u) \
-do { \
- u->inp_curr -= u->inp_ctr; \
- u->inp_ctr = 0; \
-} while (0)
-
-/* ud_inp_sess() - Returns the pointer to current session. */
-#define ud_inp_sess(u) (u->inp_sess)
-
-/* inp_cur() - Returns the current input byte. */
-#define ud_inp_curr(u) ((u)->inp_cache[(u)->inp_curr])
-
-#endif
</del></span></pre></div>
<a id="trunkSourceJavaScriptCoredisassemblerudis86udis86_synattc"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/disassembler/udis86/udis86_syn-att.c (198831 => 198832)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/disassembler/udis86/udis86_syn-att.c 2016-03-30 07:14:10 UTC (rev 198831)
+++ trunk/Source/JavaScriptCore/disassembler/udis86/udis86_syn-att.c 2016-03-30 07:17:14 UTC (rev 198832)
</span><span class="lines">@@ -23,6 +23,7 @@
</span><span class="cx"> * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
</span><span class="cx"> * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
</span><span class="cx"> */
</span><ins>+
</ins><span class="cx"> #include "config.h"
</span><span class="cx">
</span><span class="cx"> #if USE(UDIS86)
</span><span class="lines">@@ -32,6 +33,7 @@
</span><span class="cx"> #include "udis86_decode.h"
</span><span class="cx"> #include "udis86_itab.h"
</span><span class="cx"> #include "udis86_syn.h"
</span><ins>+#include "udis86_udint.h"
</ins><span class="cx">
</span><span class="cx"> /* -----------------------------------------------------------------------------
</span><span class="cx"> * opr_cast() - Prints an operand cast.
</span><span class="lines">@@ -41,9 +43,9 @@
</span><span class="cx"> opr_cast(struct ud* u, struct ud_operand* op)
</span><span class="cx"> {
</span><span class="cx"> switch(op->size) {
</span><del>- case 16 : case 32 :
- mkasm(u, "*"); break;
- default: break;
</del><ins>+ case 16 : case 32 :
+ ud_asmprintf(u, "*"); break;
+ default: break;
</ins><span class="cx"> }
</span><span class="cx"> }
</span><span class="cx">
</span><span class="lines">@@ -55,107 +57,66 @@
</span><span class="cx"> gen_operand(struct ud* u, struct ud_operand* op)
</span><span class="cx"> {
</span><span class="cx"> switch(op->type) {
</span><del>- case UD_OP_REG:
- mkasm(u, "%%%s", ud_reg_tab[op->base - UD_R_AL]);
- break;
</del><ins>+ case UD_OP_CONST:
+ ud_asmprintf(u, "$0x%x", op->lval.udword);
+ break;
</ins><span class="cx">
</span><del>- case UD_OP_MEM:
- if (u->br_far) opr_cast(u, op);
- if (u->pfx_seg)
- mkasm(u, "%%%s:", ud_reg_tab[u->pfx_seg - UD_R_AL]);
- if (op->offset == 8) {
- if (op->lval.sbyte < 0)
- mkasm(u, "-0x%x", (-op->lval.sbyte) & 0xff);
- else
- mkasm(u, "0x%x", op->lval.sbyte);
- }
- else if (op->offset == 16) {
- if (op->lval.sword < 0)
- mkasm(u, "-0x%x", (-op->lval.sword) & 0xffff);
- else
- mkasm(u, "0x%x", op->lval.sword);
- } else if (op->offset == 32) {
- if (op->lval.sdword < 0)
- mkasm(u, "-0x%x", (-op->lval.sdword) & 0xffffffff);
- else
- mkasm(u, "0x%x", op->lval.sdword);
- } else if (op->offset == 64) {
- if (op->lval.sdword < 0)
- mkasm(u, "-0x" FMT64 "x", (uint64_t)-op->lval.sqword);
- else
- mkasm(u, "0x" FMT64 "x", (uint64_t)op->lval.sqword);
- }
</del><ins>+ case UD_OP_REG:
+ ud_asmprintf(u, "%%%s", ud_reg_tab[op->base - UD_R_AL]);
+ break;
</ins><span class="cx">
</span><del>- if (op->base)
- mkasm(u, "(%%%s", ud_reg_tab[op->base - UD_R_AL]);
- if (op->index) {
- if (op->base)
- mkasm(u, ",");
- else mkasm(u, "(");
- mkasm(u, "%%%s", ud_reg_tab[op->index - UD_R_AL]);
- }
- if (op->scale)
- mkasm(u, ",%d", op->scale);
- if (op->base || op->index)
- mkasm(u, ")");
- break;
</del><ins>+ case UD_OP_MEM:
+ if (u->br_far) {
+ opr_cast(u, op);
+ }
+ if (u->pfx_seg) {
+ ud_asmprintf(u, "%%%s:", ud_reg_tab[u->pfx_seg - UD_R_AL]);
+ }
+ if (op->offset != 0) {
+ ud_syn_print_mem_disp(u, op, 0);
+ }
+ if (op->base) {
+ ud_asmprintf(u, "(%%%s", ud_reg_tab[op->base - UD_R_AL]);
+ }
+ if (op->index) {
+ if (op->base) {
+ ud_asmprintf(u, ",");
+ } else {
+ ud_asmprintf(u, "(");
+ }
+ ud_asmprintf(u, "%%%s", ud_reg_tab[op->index - UD_R_AL]);
+ }
+ if (op->scale) {
+ ud_asmprintf(u, ",%d", op->scale);
+ }
+ if (op->base || op->index) {
+ ud_asmprintf(u, ")");
+ }
+ break;
</ins><span class="cx">
</span><del>- case UD_OP_IMM: {
- int64_t imm = 0;
- uint64_t sext_mask = 0xffffffffffffffffull;
- unsigned sext_size = op->size;
</del><ins>+ case UD_OP_IMM:
+ ud_asmprintf(u, "$");
+ ud_syn_print_imm(u, op);
+ break;
</ins><span class="cx">
</span><del>- switch (op->size) {
- case 8: imm = op->lval.sbyte; break;
- case 16: imm = op->lval.sword; break;
- case 32: imm = op->lval.sdword; break;
- case 64: imm = op->lval.sqword; break;
- }
- if ( P_SEXT( u->itab_entry->prefix ) ) {
- sext_size = u->operand[ 0 ].size;
- if ( u->mnemonic == UD_Ipush )
- /* push sign-extends to operand size */
- sext_size = u->opr_mode;
- }
- if ( sext_size < 64 )
- sext_mask = ( 1ull << sext_size ) - 1;
- mkasm( u, "$0x" FMT64 "x", (uint64_t)(imm & sext_mask) );
</del><ins>+ case UD_OP_JIMM:
+ ud_syn_print_addr(u, ud_syn_rel_target(u, op));
+ break;
</ins><span class="cx">
</span><del>- break;
</del><ins>+ case UD_OP_PTR:
+ switch (op->size) {
+ case 32:
+ ud_asmprintf(u, "$0x%x, $0x%x", op->lval.ptr.seg,
+ op->lval.ptr.off & 0xFFFF);
+ break;
+ case 48:
+ ud_asmprintf(u, "$0x%x, $0x%x", op->lval.ptr.seg,
+ op->lval.ptr.off);
+ break;
</ins><span class="cx"> }
</span><del>-
- case UD_OP_JIMM:
- switch (op->size) {
- case 8:
- mkasm(u, "0x" FMT64 "x", (uint64_t)(u->pc + op->lval.sbyte));
- break;
- case 16:
- mkasm(u, "0x" FMT64 "x", (uint64_t)((u->pc + op->lval.sword) & 0xffff) );
- break;
- case 32:
- if (u->dis_mode == 32)
- mkasm(u, "0x" FMT64 "x", (uint64_t)((u->pc + op->lval.sdword) & 0xffffffff));
- else
- mkasm(u, "0x" FMT64 "x", (uint64_t)(u->pc + op->lval.sdword));
- break;
- default:break;
- }
- break;
-
- case UD_OP_PTR:
- switch (op->size) {
- case 32:
- mkasm(u, "$0x%x, $0x%x", op->lval.ptr.seg,
- op->lval.ptr.off & 0xFFFF);
- break;
- case 48:
- mkasm(u, "$0x%x, $0x%lx", op->lval.ptr.seg,
- (unsigned long)op->lval.ptr.off);
- break;
- }
- break;
-
- default: return;
</del><ins>+ break;
+
+ default: return;
</ins><span class="cx"> }
</span><span class="cx"> }
</span><span class="cx">
</span><span class="lines">@@ -167,99 +128,108 @@
</span><span class="cx"> ud_translate_att(struct ud *u)
</span><span class="cx"> {
</span><span class="cx"> int size = 0;
</span><del>- unsigned i;
</del><ins>+ int star = 0;
</ins><span class="cx">
</span><span class="cx"> /* check if P_OSO prefix is used */
</span><span class="cx"> if (! P_OSO(u->itab_entry->prefix) && u->pfx_opr) {
</span><del>- switch (u->dis_mode) {
- case 16:
- mkasm(u, "o32 ");
- break;
- case 32:
- case 64:
- mkasm(u, "o16 ");
- break;
- }
</del><ins>+ switch (u->dis_mode) {
+ case 16:
+ ud_asmprintf(u, "o32 ");
+ break;
+ case 32:
+ case 64:
+ ud_asmprintf(u, "o16 ");
+ break;
</ins><span class="cx"> }
</span><ins>+ }
</ins><span class="cx">
</span><span class="cx"> /* check if P_ASO prefix was used */
</span><span class="cx"> if (! P_ASO(u->itab_entry->prefix) && u->pfx_adr) {
</span><del>- switch (u->dis_mode) {
- case 16:
- mkasm(u, "a32 ");
- break;
- case 32:
- mkasm(u, "a16 ");
- break;
- case 64:
- mkasm(u, "a32 ");
- break;
- }
</del><ins>+ switch (u->dis_mode) {
+ case 16:
+ ud_asmprintf(u, "a32 ");
+ break;
+ case 32:
+ ud_asmprintf(u, "a16 ");
+ break;
+ case 64:
+ ud_asmprintf(u, "a32 ");
+ break;
</ins><span class="cx"> }
</span><ins>+ }
</ins><span class="cx">
</span><span class="cx"> if (u->pfx_lock)
</span><del>- mkasm(u, "lock ");
- if (u->pfx_rep)
- mkasm(u, "rep ");
- if (u->pfx_repne)
- mkasm(u, "repne ");
</del><ins>+ ud_asmprintf(u, "lock ");
+ if (u->pfx_rep) {
+ ud_asmprintf(u, "rep ");
+ } else if (u->pfx_repe) {
+ ud_asmprintf(u, "repe ");
+ } else if (u->pfx_repne) {
+ ud_asmprintf(u, "repne ");
+ }
</ins><span class="cx">
</span><span class="cx"> /* special instructions */
</span><span class="cx"> switch (u->mnemonic) {
</span><del>- case UD_Iretf:
- mkasm(u, "lret ");
- break;
- case UD_Idb:
- mkasm(u, ".byte 0x%x", u->operand[0].lval.ubyte);
- return;
- case UD_Ijmp:
- case UD_Icall:
- if (u->br_far) mkasm(u, "l");
- mkasm(u, "%s", ud_lookup_mnemonic(u->mnemonic));
- break;
- case UD_Ibound:
- case UD_Ienter:
- if (u->operand[0].type != UD_NONE)
- gen_operand(u, &u->operand[0]);
- if (u->operand[1].type != UD_NONE) {
- mkasm(u, ",");
- gen_operand(u, &u->operand[1]);
- }
- return;
- default:
- mkasm(u, "%s", ud_lookup_mnemonic(u->mnemonic));
</del><ins>+ case UD_Iretf:
+ ud_asmprintf(u, "lret ");
+ break;
+ case UD_Idb:
+ ud_asmprintf(u, ".byte 0x%x", u->operand[0].lval.ubyte);
+ return;
+ case UD_Ijmp:
+ case UD_Icall:
+ if (u->br_far) ud_asmprintf(u, "l");
+ if (u->operand[0].type == UD_OP_REG) {
+ star = 1;
+ }
+ ud_asmprintf(u, "%s", ud_lookup_mnemonic(u->mnemonic));
+ break;
+ case UD_Ibound:
+ case UD_Ienter:
+ if (u->operand[0].type != UD_NONE)
+ gen_operand(u, &u->operand[0]);
+ if (u->operand[1].type != UD_NONE) {
+ ud_asmprintf(u, ",");
+ gen_operand(u, &u->operand[1]);
+ }
+ return;
+ default:
+ ud_asmprintf(u, "%s", ud_lookup_mnemonic(u->mnemonic));
</ins><span class="cx"> }
</span><span class="cx">
</span><del>- for (i = 3; i--;) {
- if (u->operand[i].size > size
- && u->operand[i].type != UD_OP_JIMM)
- size = u->operand[i].size;
</del><ins>+ if (size == 8) {
+ ud_asmprintf(u, "b");
+ } else if (size == 16) {
+ ud_asmprintf(u, "w");
+ } else if (size == 64) {
+ ud_asmprintf(u, "q");
</ins><span class="cx"> }
</span><span class="cx">
</span><del>- if (size == 8)
- mkasm(u, "b");
- else if (size == 16)
- mkasm(u, "w");
- else if (size == 32)
- mkasm(u, "l");
- else if (size == 64)
- mkasm(u, "q");
</del><ins>+ if (star) {
+ ud_asmprintf(u, " *");
+ } else {
+ ud_asmprintf(u, " ");
+ }
</ins><span class="cx">
</span><del>- mkasm(u, " ");
-
</del><ins>+ if (u->operand[3].type != UD_NONE) {
+ gen_operand(u, &u->operand[3]);
+ ud_asmprintf(u, ", ");
+ }
</ins><span class="cx"> if (u->operand[2].type != UD_NONE) {
</span><del>- gen_operand(u, &u->operand[2]);
- mkasm(u, ", ");
</del><ins>+ gen_operand(u, &u->operand[2]);
+ ud_asmprintf(u, ", ");
</ins><span class="cx"> }
</span><del>-
</del><span class="cx"> if (u->operand[1].type != UD_NONE) {
</span><del>- gen_operand(u, &u->operand[1]);
- mkasm(u, ", ");
</del><ins>+ gen_operand(u, &u->operand[1]);
+ ud_asmprintf(u, ", ");
</ins><span class="cx"> }
</span><del>-
- if (u->operand[0].type != UD_NONE)
- gen_operand(u, &u->operand[0]);
</del><ins>+ if (u->operand[0].type != UD_NONE) {
+ gen_operand(u, &u->operand[0]);
+ }
</ins><span class="cx"> }
</span><span class="cx">
</span><span class="cx"> #endif // USE(UDIS86)
</span><span class="cx">
</span><ins>+/*
+vim: set ts=2 sw=2 expandtab
+*/
</ins></span></pre></div>
<a id="trunkSourceJavaScriptCoredisassemblerudis86udis86_synintelc"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/disassembler/udis86/udis86_syn-intel.c (198831 => 198832)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/disassembler/udis86/udis86_syn-intel.c 2016-03-30 07:14:10 UTC (rev 198831)
+++ trunk/Source/JavaScriptCore/disassembler/udis86/udis86_syn-intel.c 2016-03-30 07:17:14 UTC (rev 198832)
</span><span class="lines">@@ -1,6 +1,6 @@
</span><span class="cx"> /* udis86 - libudis86/syn-intel.c
</span><span class="cx"> *
</span><del>- * Copyright (c) 2002-2009 Vivek Thampi
</del><ins>+ * Copyright (c) 2002-2013 Vivek Thampi
</ins><span class="cx"> * All rights reserved.
</span><span class="cx"> *
</span><span class="cx"> * Redistribution and use in source and binary forms, with or without modification,
</span><span class="lines">@@ -23,6 +23,7 @@
</span><span class="cx"> * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
</span><span class="cx"> * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
</span><span class="cx"> */
</span><ins>+
</ins><span class="cx"> #include "config.h"
</span><span class="cx">
</span><span class="cx"> #if USE(UDIS86)
</span><span class="lines">@@ -32,6 +33,7 @@
</span><span class="cx"> #include "udis86_decode.h"
</span><span class="cx"> #include "udis86_itab.h"
</span><span class="cx"> #include "udis86_syn.h"
</span><ins>+#include "udis86_udint.h"
</ins><span class="cx">
</span><span class="cx"> /* -----------------------------------------------------------------------------
</span><span class="cx"> * opr_cast() - Prints an operand cast.
</span><span class="lines">@@ -40,16 +42,19 @@
</span><span class="cx"> static void
</span><span class="cx"> opr_cast(struct ud* u, struct ud_operand* op)
</span><span class="cx"> {
</span><ins>+ if (u->br_far) {
+ ud_asmprintf(u, "far ");
+ }
</ins><span class="cx"> switch(op->size) {
</span><del>- case 8: mkasm(u, "byte " ); break;
- case 16: mkasm(u, "word " ); break;
- case 32: mkasm(u, "dword "); break;
- case 64: mkasm(u, "qword "); break;
- case 80: mkasm(u, "tword "); break;
- default: break;
</del><ins>+ case 8: ud_asmprintf(u, "byte " ); break;
+ case 16: ud_asmprintf(u, "word " ); break;
+ case 32: ud_asmprintf(u, "dword "); break;
+ case 64: ud_asmprintf(u, "qword "); break;
+ case 80: ud_asmprintf(u, "tword "); break;
+ case 128: ud_asmprintf(u, "oword "); break;
+ case 256: ud_asmprintf(u, "yword "); break;
+ default: break;
</ins><span class="cx"> }
</span><del>- if (u->br_far)
- mkasm(u, "far ");
</del><span class="cx"> }
</span><span class="cx">
</span><span class="cx"> /* -----------------------------------------------------------------------------
</span><span class="lines">@@ -59,121 +64,63 @@
</span><span class="cx"> static void gen_operand(struct ud* u, struct ud_operand* op, int syn_cast)
</span><span class="cx"> {
</span><span class="cx"> switch(op->type) {
</span><del>- case UD_OP_REG:
- mkasm(u, "%s", ud_reg_tab[op->base - UD_R_AL]);
- break;
</del><ins>+ case UD_OP_REG:
+ ud_asmprintf(u, "%s", ud_reg_tab[op->base - UD_R_AL]);
+ break;
</ins><span class="cx">
</span><del>- case UD_OP_MEM: {
</del><ins>+ case UD_OP_MEM:
+ if (syn_cast) {
+ opr_cast(u, op);
+ }
+ ud_asmprintf(u, "[");
+ if (u->pfx_seg) {
+ ud_asmprintf(u, "%s:", ud_reg_tab[u->pfx_seg - UD_R_AL]);
+ }
+ if (op->base) {
+ ud_asmprintf(u, "%s", ud_reg_tab[op->base - UD_R_AL]);
+ }
+ if (op->index) {
+ ud_asmprintf(u, "%s%s", op->base != UD_NONE? "+" : "",
+ ud_reg_tab[op->index - UD_R_AL]);
+ if (op->scale) {
+ ud_asmprintf(u, "*%d", op->scale);
+ }
+ }
+ if (op->offset != 0) {
+ ud_syn_print_mem_disp(u, op, (op->base != UD_NONE ||
+ op->index != UD_NONE) ? 1 : 0);
+ }
+ ud_asmprintf(u, "]");
+ break;
+
+ case UD_OP_IMM:
+ ud_syn_print_imm(u, op);
+ break;
</ins><span class="cx">
</span><del>- int op_f = 0;
</del><span class="cx">
</span><del>- if (syn_cast)
- opr_cast(u, op);
</del><ins>+ case UD_OP_JIMM:
+ ud_syn_print_addr(u, ud_syn_rel_target(u, op));
+ break;
</ins><span class="cx">
</span><del>- mkasm(u, "[");
-
- if (u->pfx_seg)
- mkasm(u, "%s:", ud_reg_tab[u->pfx_seg - UD_R_AL]);
-
- if (op->base) {
- mkasm(u, "%s", ud_reg_tab[op->base - UD_R_AL]);
- op_f = 1;
- }
-
- if (op->index) {
- if (op_f)
- mkasm(u, "+");
- mkasm(u, "%s", ud_reg_tab[op->index - UD_R_AL]);
- op_f = 1;
- }
-
- if (op->scale)
- mkasm(u, "*%d", op->scale);
-
- if (op->offset == 8) {
- if (op->lval.sbyte < 0)
- mkasm(u, "-0x%x", -op->lval.sbyte);
- else mkasm(u, "%s0x%x", (op_f) ? "+" : "", op->lval.sbyte);
- }
- else if (op->offset == 16)
- mkasm(u, "%s0x%x", (op_f) ? "+" : "", op->lval.uword);
- else if (op->offset == 32) {
- if (u->adr_mode == 64) {
- if (op->lval.sdword < 0)
- mkasm(u, "-0x%x", -op->lval.sdword);
- else mkasm(u, "%s0x%x", (op_f) ? "+" : "", op->lval.sdword);
- }
- else mkasm(u, "%s0x%lx", (op_f) ? "+" : "", (unsigned long)op->lval.udword);
- }
- else if (op->offset == 64)
- mkasm(u, "%s0x" FMT64 "x", (op_f) ? "+" : "", (uint64_t)op->lval.uqword);
-
- mkasm(u, "]");
- break;
- }
-
- case UD_OP_IMM: {
- int64_t imm = 0;
- uint64_t sext_mask = 0xffffffffffffffffull;
- unsigned sext_size = op->size;
-
- if (syn_cast)
- opr_cast(u, op);
- switch (op->size) {
- case 8: imm = op->lval.sbyte; break;
- case 16: imm = op->lval.sword; break;
- case 32: imm = op->lval.sdword; break;
- case 64: imm = op->lval.sqword; break;
- }
- if ( P_SEXT( u->itab_entry->prefix ) ) {
- sext_size = u->operand[ 0 ].size;
- if ( u->mnemonic == UD_Ipush )
- /* push sign-extends to operand size */
- sext_size = u->opr_mode;
- }
- if ( sext_size < 64 )
- sext_mask = ( 1ull << sext_size ) - 1;
- mkasm( u, "0x" FMT64 "x", (uint64_t)(imm & sext_mask) );
-
- break;
</del><ins>+ case UD_OP_PTR:
+ switch (op->size) {
+ case 32:
+ ud_asmprintf(u, "word 0x%x:0x%x", op->lval.ptr.seg,
+ op->lval.ptr.off & 0xFFFF);
+ break;
+ case 48:
+ ud_asmprintf(u, "dword 0x%x:0x%x", op->lval.ptr.seg,
+ op->lval.ptr.off);
+ break;
</ins><span class="cx"> }
</span><ins>+ break;
</ins><span class="cx">
</span><ins>+ case UD_OP_CONST:
+ if (syn_cast) opr_cast(u, op);
+ ud_asmprintf(u, "%d", op->lval.udword);
+ break;
</ins><span class="cx">
</span><del>- case UD_OP_JIMM:
- if (syn_cast) opr_cast(u, op);
- switch (op->size) {
- case 8:
- mkasm(u, "0x" FMT64 "x", (uint64_t)(u->pc + op->lval.sbyte));
- break;
- case 16:
- mkasm(u, "0x" FMT64 "x", (uint64_t)(( u->pc + op->lval.sword ) & 0xffff) );
- break;
- case 32:
- mkasm(u, "0x" FMT64 "x", (uint64_t)(( u->pc + op->lval.sdword ) & 0xfffffffful) );
- break;
- default:break;
- }
- break;
-
- case UD_OP_PTR:
- switch (op->size) {
- case 32:
- mkasm(u, "word 0x%x:0x%x", op->lval.ptr.seg,
- op->lval.ptr.off & 0xFFFF);
- break;
- case 48:
- mkasm(u, "dword 0x%x:0x%lx", op->lval.ptr.seg,
- (unsigned long)op->lval.ptr.off);
- break;
- }
- break;
-
- case UD_OP_CONST:
- if (syn_cast) opr_cast(u, op);
- mkasm(u, "%d", op->lval.udword);
- break;
-
- default: return;
</del><ins>+ default: return;
</ins><span class="cx"> }
</span><span class="cx"> }
</span><span class="cx">
</span><span class="lines">@@ -181,98 +128,104 @@
</span><span class="cx"> * translates to intel syntax
</span><span class="cx"> * =============================================================================
</span><span class="cx"> */
</span><del>-extern void ud_translate_intel(struct ud* u)
</del><ins>+extern void
+ud_translate_intel(struct ud* u)
</ins><span class="cx"> {
</span><del>- /* -- prefixes -- */
-
</del><span class="cx"> /* check if P_OSO prefix is used */
</span><del>- if (! P_OSO(u->itab_entry->prefix) && u->pfx_opr) {
- switch (u->dis_mode) {
- case 16:
- mkasm(u, "o32 ");
- break;
- case 32:
- case 64:
- mkasm(u, "o16 ");
- break;
- }
</del><ins>+ if (!P_OSO(u->itab_entry->prefix) && u->pfx_opr) {
+ switch (u->dis_mode) {
+ case 16: ud_asmprintf(u, "o32 "); break;
+ case 32:
+ case 64: ud_asmprintf(u, "o16 "); break;
+ }
</ins><span class="cx"> }
</span><span class="cx">
</span><span class="cx"> /* check if P_ASO prefix was used */
</span><del>- if (! P_ASO(u->itab_entry->prefix) && u->pfx_adr) {
- switch (u->dis_mode) {
- case 16:
- mkasm(u, "a32 ");
- break;
- case 32:
- mkasm(u, "a16 ");
- break;
- case 64:
- mkasm(u, "a32 ");
- break;
- }
</del><ins>+ if (!P_ASO(u->itab_entry->prefix) && u->pfx_adr) {
+ switch (u->dis_mode) {
+ case 16: ud_asmprintf(u, "a32 "); break;
+ case 32: ud_asmprintf(u, "a16 "); break;
+ case 64: ud_asmprintf(u, "a32 "); break;
+ }
</ins><span class="cx"> }
</span><span class="cx">
</span><del>- if ( u->pfx_seg &&
- u->operand[0].type != UD_OP_MEM &&
- u->operand[1].type != UD_OP_MEM ) {
- mkasm(u, "%s ", ud_reg_tab[u->pfx_seg - UD_R_AL]);
- }
- if (u->pfx_lock)
- mkasm(u, "lock ");
- if (u->pfx_rep)
- mkasm(u, "rep ");
- if (u->pfx_repne)
- mkasm(u, "repne ");
</del><ins>+ if (u->pfx_seg &&
+ u->operand[0].type != UD_OP_MEM &&
+ u->operand[1].type != UD_OP_MEM ) {
+ ud_asmprintf(u, "%s ", ud_reg_tab[u->pfx_seg - UD_R_AL]);
+ }
</ins><span class="cx">
</span><ins>+ if (u->pfx_lock) {
+ ud_asmprintf(u, "lock ");
+ }
+ if (u->pfx_rep) {
+ ud_asmprintf(u, "rep ");
+ } else if (u->pfx_repe) {
+ ud_asmprintf(u, "repe ");
+ } else if (u->pfx_repne) {
+ ud_asmprintf(u, "repne ");
+ }
+
</ins><span class="cx"> /* print the instruction mnemonic */
</span><del>- mkasm(u, "%s ", ud_lookup_mnemonic(u->mnemonic));
</del><ins>+ ud_asmprintf(u, "%s", ud_lookup_mnemonic(u->mnemonic));
</ins><span class="cx">
</span><del>- /* operand 1 */
</del><span class="cx"> if (u->operand[0].type != UD_NONE) {
</span><span class="cx"> int cast = 0;
</span><del>- if ( u->operand[0].type == UD_OP_IMM &&
- u->operand[1].type == UD_NONE )
- cast = u->c1;
- if ( u->operand[0].type == UD_OP_MEM ) {
- cast = u->c1;
- if ( u->operand[1].type == UD_OP_IMM ||
- u->operand[1].type == UD_OP_CONST )
- cast = 1;
- if ( u->operand[1].type == UD_NONE )
- cast = 1;
- if ( ( u->operand[0].size != u->operand[1].size ) && u->operand[1].size )
- cast = 1;
- } else if ( u->operand[ 0 ].type == UD_OP_JIMM ) {
- if ( u->operand[ 0 ].size > 8 ) cast = 1;
</del><ins>+ ud_asmprintf(u, " ");
+ if (u->operand[0].type == UD_OP_MEM) {
+ if (u->operand[1].type == UD_OP_IMM ||
+ u->operand[1].type == UD_OP_CONST ||
+ u->operand[1].type == UD_NONE ||
+ (u->operand[0].size != u->operand[1].size)) {
+ cast = 1;
+ } else if (u->operand[1].type == UD_OP_REG &&
+ u->operand[1].base == UD_R_CL) {
+ switch (u->mnemonic) {
+ case UD_Ircl:
+ case UD_Irol:
+ case UD_Iror:
+ case UD_Ircr:
+ case UD_Ishl:
+ case UD_Ishr:
+ case UD_Isar:
+ cast = 1;
+ break;
+ default: break;
+ }
+ }
</ins><span class="cx"> }
</span><del>- gen_operand(u, &u->operand[0], cast);
</del><ins>+ gen_operand(u, &u->operand[0], cast);
</ins><span class="cx"> }
</span><del>- /* operand 2 */
</del><ins>+
</ins><span class="cx"> if (u->operand[1].type != UD_NONE) {
</span><span class="cx"> int cast = 0;
</span><del>- mkasm(u, ", ");
- if ( u->operand[1].type == UD_OP_MEM ) {
- cast = u->c1;
-
- if ( u->operand[0].type != UD_OP_REG )
- cast = 1;
- if ( u->operand[0].size != u->operand[1].size && u->operand[1].size )
- cast = 1;
- if ( u->operand[0].type == UD_OP_REG &&
- u->operand[0].base >= UD_R_ES &&
- u->operand[0].base <= UD_R_GS )
- cast = 0;
</del><ins>+ ud_asmprintf(u, ", ");
+ if (u->operand[1].type == UD_OP_MEM &&
+ u->operand[0].size != u->operand[1].size &&
+ !ud_opr_is_sreg(&u->operand[0])) {
+ cast = 1;
</ins><span class="cx"> }
</span><del>- gen_operand(u, &u->operand[1], cast );
</del><ins>+ gen_operand(u, &u->operand[1], cast);
</ins><span class="cx"> }
</span><span class="cx">
</span><del>- /* operand 3 */
</del><span class="cx"> if (u->operand[2].type != UD_NONE) {
</span><del>- mkasm(u, ", ");
- gen_operand(u, &u->operand[2], u->c3);
</del><ins>+ int cast = 0;
+ ud_asmprintf(u, ", ");
+ if (u->operand[2].type == UD_OP_MEM &&
+ u->operand[2].size != u->operand[1].size) {
+ cast = 1;
+ }
+ gen_operand(u, &u->operand[2], cast);
</ins><span class="cx"> }
</span><ins>+
+ if (u->operand[3].type != UD_NONE) {
+ ud_asmprintf(u, ", ");
+ gen_operand(u, &u->operand[3], 0);
+ }
</ins><span class="cx"> }
</span><span class="cx">
</span><span class="cx"> #endif // USE(UDIS86)
</span><span class="cx">
</span><ins>+/*
+vim: set ts=2 sw=2 expandtab
+*/
</ins></span></pre></div>
<a id="trunkSourceJavaScriptCoredisassemblerudis86udis86_sync"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/disassembler/udis86/udis86_syn.c (198831 => 198832)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/disassembler/udis86/udis86_syn.c 2016-03-30 07:14:10 UTC (rev 198831)
+++ trunk/Source/JavaScriptCore/disassembler/udis86/udis86_syn.c 2016-03-30 07:17:14 UTC (rev 198832)
</span><span class="lines">@@ -1,6 +1,6 @@
</span><span class="cx"> /* udis86 - libudis86/syn.c
</span><span class="cx"> *
</span><del>- * Copyright (c) 2002-2009 Vivek Thampi
</del><ins>+ * Copyright (c) 2002-2013 Vivek Thampi
</ins><span class="cx"> * All rights reserved.
</span><span class="cx"> *
</span><span class="cx"> * Redistribution and use in source and binary forms, with or without modification,
</span><span class="lines">@@ -28,59 +28,192 @@
</span><span class="cx">
</span><span class="cx"> #if USE(UDIS86)
</span><span class="cx">
</span><del>-/* -----------------------------------------------------------------------------
- * Intel Register Table - Order Matters (types.h)!
- * -----------------------------------------------------------------------------
</del><ins>+#include "udis86_types.h"
+#include "udis86_decode.h"
+#include "udis86_syn.h"
+#include "udis86_udint.h"
+
+/*
+ * Register Table - Order Matters (types.h)!
+ *
</ins><span class="cx"> */
</span><span class="cx"> const char* ud_reg_tab[] =
</span><span class="cx"> {
</span><del>- "al", "cl", "dl", "bl",
- "ah", "ch", "dh", "bh",
- "spl", "bpl", "sil", "dil",
- "r8b", "r9b", "r10b", "r11b",
- "r12b", "r13b", "r14b", "r15b",
</del><ins>+ "al", "cl", "dl", "bl",
+ "ah", "ch", "dh", "bh",
+ "spl", "bpl", "sil", "dil",
+ "r8b", "r9b", "r10b", "r11b",
+ "r12b", "r13b", "r14b", "r15b",
</ins><span class="cx">
</span><del>- "ax", "cx", "dx", "bx",
- "sp", "bp", "si", "di",
- "r8w", "r9w", "r10w", "r11w",
- "r12w", "r13W" , "r14w", "r15w",
-
- "eax", "ecx", "edx", "ebx",
- "esp", "ebp", "esi", "edi",
- "r8d", "r9d", "r10d", "r11d",
- "r12d", "r13d", "r14d", "r15d",
-
- "rax", "rcx", "rdx", "rbx",
- "rsp", "rbp", "rsi", "rdi",
- "r8", "r9", "r10", "r11",
- "r12", "r13", "r14", "r15",
</del><ins>+ "ax", "cx", "dx", "bx",
+ "sp", "bp", "si", "di",
+ "r8w", "r9w", "r10w", "r11w",
+ "r12w", "r13w", "r14w", "r15w",
+
+ "eax", "ecx", "edx", "ebx",
+ "esp", "ebp", "esi", "edi",
+ "r8d", "r9d", "r10d", "r11d",
+ "r12d", "r13d", "r14d", "r15d",
+
+ "rax", "rcx", "rdx", "rbx",
+ "rsp", "rbp", "rsi", "rdi",
+ "r8", "r9", "r10", "r11",
+ "r12", "r13", "r14", "r15",
</ins><span class="cx">
</span><del>- "es", "cs", "ss", "ds",
- "fs", "gs",
</del><ins>+ "es", "cs", "ss", "ds",
+ "fs", "gs",
</ins><span class="cx">
</span><del>- "cr0", "cr1", "cr2", "cr3",
- "cr4", "cr5", "cr6", "cr7",
- "cr8", "cr9", "cr10", "cr11",
- "cr12", "cr13", "cr14", "cr15",
-
- "dr0", "dr1", "dr2", "dr3",
- "dr4", "dr5", "dr6", "dr7",
- "dr8", "dr9", "dr10", "dr11",
- "dr12", "dr13", "dr14", "dr15",
</del><ins>+ "cr0", "cr1", "cr2", "cr3",
+ "cr4", "cr5", "cr6", "cr7",
+ "cr8", "cr9", "cr10", "cr11",
+ "cr12", "cr13", "cr14", "cr15",
+
+ "dr0", "dr1", "dr2", "dr3",
+ "dr4", "dr5", "dr6", "dr7",
+ "dr8", "dr9", "dr10", "dr11",
+ "dr12", "dr13", "dr14", "dr15",
</ins><span class="cx">
</span><del>- "mm0", "mm1", "mm2", "mm3",
- "mm4", "mm5", "mm6", "mm7",
</del><ins>+ "mm0", "mm1", "mm2", "mm3",
+ "mm4", "mm5", "mm6", "mm7",
</ins><span class="cx">
</span><del>- "st0", "st1", "st2", "st3",
- "st4", "st5", "st6", "st7",
</del><ins>+ "st0", "st1", "st2", "st3",
+ "st4", "st5", "st6", "st7",
</ins><span class="cx">
</span><del>- "xmm0", "xmm1", "xmm2", "xmm3",
- "xmm4", "xmm5", "xmm6", "xmm7",
- "xmm8", "xmm9", "xmm10", "xmm11",
- "xmm12", "xmm13", "xmm14", "xmm15",
</del><ins>+ "xmm0", "xmm1", "xmm2", "xmm3",
+ "xmm4", "xmm5", "xmm6", "xmm7",
+ "xmm8", "xmm9", "xmm10", "xmm11",
+ "xmm12", "xmm13", "xmm14", "xmm15",
</ins><span class="cx">
</span><ins>+ "ymm0", "ymm1", "ymm2", "ymm3",
+ "ymm4", "ymm5", "ymm6", "ymm7",
+ "ymm8", "ymm9", "ymm10", "ymm11",
+ "ymm12", "ymm13", "ymm14", "ymm15",
+
</ins><span class="cx"> "rip"
</span><span class="cx"> };
</span><span class="cx">
</span><ins>+
+uint64_t
+ud_syn_rel_target(struct ud *u, struct ud_operand *opr)
+{
+ const uint64_t trunc_mask = 0xffffffffffffffffull >> (64 - u->opr_mode);
+ switch (opr->size) {
+ case 8 : return (u->pc + opr->lval.sbyte) & trunc_mask;
+ case 16: return (u->pc + opr->lval.sword) & trunc_mask;
+ case 32: return (u->pc + opr->lval.sdword) & trunc_mask;
+ default: UD_ASSERT(!"invalid relative offset size.");
+ return 0ull;
+ }
+}
+
+
+/*
+ * asmprintf
+ * Printf style function for printing translated assembly
+ * output. Returns the number of characters written and
+ * moves the buffer pointer forward. On an overflow,
+ * returns a negative number and truncates the output.
+ */
+int
+ud_asmprintf(struct ud *u, const char *fmt, ...)
+{
+ int ret;
+ int avail;
+ va_list ap;
+ va_start(ap, fmt);
+ avail = u->asm_buf_size - u->asm_buf_fill - 1 /* nullchar */;
+ ret = vsnprintf((char*) u->asm_buf + u->asm_buf_fill, avail, fmt, ap);
+ if (ret < 0 || ret > avail) {
+ u->asm_buf_fill = u->asm_buf_size - 1;
+ } else {
+ u->asm_buf_fill += ret;
+ }
+ va_end(ap);
+ return ret;
+}
+
+
+void
+ud_syn_print_addr(struct ud *u, uint64_t addr)
+{
+ const char *name = NULL;
+ if (u->sym_resolver) {
+ int64_t offset = 0;
+ name = u->sym_resolver(u, addr, &offset);
+ if (name) {
+ if (offset) {
+ ud_asmprintf(u, "%s%+" FMT64 "d", name, offset);
+ } else {
+ ud_asmprintf(u, "%s", name);
+ }
+ return;
+ }
+ }
+ ud_asmprintf(u, "0x%" FMT64 "x", addr);
+}
+
+
+void
+ud_syn_print_imm(struct ud* u, const struct ud_operand *op)
+{
+ uint64_t v;
+ if (op->_oprcode == OP_sI && op->size != u->opr_mode) {
+ if (op->size == 8) {
+ v = (int64_t)op->lval.sbyte;
+ } else {
+ UD_ASSERT(op->size == 32);
+ v = (int64_t)op->lval.sdword;
+ }
+ if (u->opr_mode < 64) {
+ v = v & ((1ull << u->opr_mode) - 1ull);
+ }
+ } else {
+ switch (op->size) {
+ case 8 : v = op->lval.ubyte; break;
+ case 16: v = op->lval.uword; break;
+ case 32: v = op->lval.udword; break;
+ case 64: v = op->lval.uqword; break;
+ default: UD_ASSERT(!"invalid offset"); v = 0; /* keep cc happy */
+ }
+ }
+ ud_asmprintf(u, "0x%" FMT64 "x", v);
+}
+
+
+void
+ud_syn_print_mem_disp(struct ud* u, const struct ud_operand *op, int sign)
+{
+ UD_ASSERT(op->offset != 0);
+ if (op->base == UD_NONE && op->index == UD_NONE) {
+ uint64_t v;
+ UD_ASSERT(op->scale == UD_NONE && op->offset != 8);
+ /* unsigned mem-offset */
+ switch (op->offset) {
+ case 16: v = op->lval.uword; break;
+ case 32: v = op->lval.udword; break;
+ case 64: v = op->lval.uqword; break;
+ default: UD_ASSERT(!"invalid offset"); v = 0; /* keep cc happy */
+ }
+ ud_asmprintf(u, "0x%" FMT64 "x", v);
+ } else {
+ int64_t v;
+ UD_ASSERT(op->offset != 64);
+ switch (op->offset) {
+ case 8 : v = op->lval.sbyte; break;
+ case 16: v = op->lval.sword; break;
+ case 32: v = op->lval.sdword; break;
+ default: UD_ASSERT(!"invalid offset"); v = 0; /* keep cc happy */
+ }
+ if (v < 0) {
+ ud_asmprintf(u, "-0x%" FMT64 "x", -v);
+ } else if (v > 0) {
+ ud_asmprintf(u, "%s0x%" FMT64 "x", sign? "+" : "", v);
+ }
+ }
+}
+
</ins><span class="cx"> #endif // USE(UDIS86)
</span><span class="cx">
</span><ins>+/*
+vim: set ts=2 sw=2 expandtab
+*/
</ins></span></pre></div>
<a id="trunkSourceJavaScriptCoredisassemblerudis86udis86_synh"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/disassembler/udis86/udis86_syn.h (198831 => 198832)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/disassembler/udis86/udis86_syn.h 2016-03-30 07:14:10 UTC (rev 198831)
+++ trunk/Source/JavaScriptCore/disassembler/udis86/udis86_syn.h 2016-03-30 07:17:14 UTC (rev 198832)
</span><span class="lines">@@ -27,21 +27,27 @@
</span><span class="cx"> #define UD_SYN_H
</span><span class="cx">
</span><span class="cx"> #include "udis86_types.h"
</span><del>-#include <wtf/Assertions.h>
-
</del><span class="cx"> #ifndef __UD_STANDALONE__
</span><span class="cx"> # include <stdarg.h>
</span><span class="cx"> #endif /* __UD_STANDALONE__ */
</span><span class="cx">
</span><span class="cx"> extern const char* ud_reg_tab[];
</span><span class="cx">
</span><del>-static void mkasm(struct ud* u, const char* fmt, ...) WTF_ATTRIBUTE_PRINTF(2, 3);
-static void mkasm(struct ud* u, const char* fmt, ...)
-{
- va_list ap;
- va_start(ap, fmt);
- u->insn_fill += vsnprintf((char*) u->insn_buffer + u->insn_fill, UD_STRING_BUFFER_SIZE - u->insn_fill, fmt, ap);
- va_end(ap);
-}
</del><ins>+uint64_t ud_syn_rel_target(struct ud*, struct ud_operand*);
</ins><span class="cx">
</span><ins>+#ifdef __GNUC__
+int ud_asmprintf(struct ud *u, const char *fmt, ...)
+ __attribute__ ((format (printf, 2, 3)));
+#else
+int ud_asmprintf(struct ud *u, const char *fmt, ...);
</ins><span class="cx"> #endif
</span><ins>+
+void ud_syn_print_addr(struct ud *u, uint64_t addr);
+void ud_syn_print_imm(struct ud* u, const struct ud_operand *op);
+void ud_syn_print_mem_disp(struct ud* u, const struct ud_operand *, int sign);
+
+#endif /* UD_SYN_H */
+
+/*
+vim: set ts=2 sw=2 expandtab
+*/
</ins></span></pre></div>
<a id="trunkSourceJavaScriptCoredisassemblerudis86udis86_typesh"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/disassembler/udis86/udis86_types.h (198831 => 198832)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/disassembler/udis86/udis86_types.h 2016-03-30 07:14:10 UTC (rev 198831)
+++ trunk/Source/JavaScriptCore/disassembler/udis86/udis86_types.h 2016-03-30 07:17:14 UTC (rev 198832)
</span><span class="lines">@@ -1,6 +1,6 @@
</span><span class="cx"> /* udis86 - libudis86/types.h
</span><span class="cx"> *
</span><del>- * Copyright (c) 2002-2009 Vivek Thampi
</del><ins>+ * Copyright (c) 2002-2013 Vivek Thampi
</ins><span class="cx"> * All rights reserved.
</span><span class="cx"> *
</span><span class="cx"> * Redistribution and use in source and binary forms, with or without modification,
</span><span class="lines">@@ -26,9 +26,23 @@
</span><span class="cx"> #ifndef UD_TYPES_H
</span><span class="cx"> #define UD_TYPES_H
</span><span class="cx">
</span><del>-#ifndef __UD_STANDALONE__
</del><ins>+#ifdef __KERNEL__
+ /*
+ * -D__KERNEL__ is automatically passed on the command line when
+ * building something as part of the Linux kernel. Assume standalone
+ * mode.
+ */
+# include <linux/kernel.h>
+# include <linux/string.h>
+# ifndef __UD_STANDALONE__
+# define __UD_STANDALONE__ 1
+# endif
+#endif /* __KERNEL__ */
+
+#if !defined(__UD_STANDALONE__)
+# include <stdint.h>
</ins><span class="cx"> # include <stdio.h>
</span><del>-#endif /* __UD_STANDALONE__ */
</del><ins>+#endif
</ins><span class="cx">
</span><span class="cx"> /* gcc specific extensions */
</span><span class="cx"> #ifdef __GNUC__
</span><span class="lines">@@ -37,26 +51,6 @@
</span><span class="cx"> # define UD_ATTR_PACKED
</span><span class="cx"> #endif /* UD_ATTR_PACKED */
</span><span class="cx">
</span><del>-#ifdef _MSC_VER
-# define FMT64 "%I64"
- typedef unsigned __int8 uint8_t;
- typedef unsigned __int16 uint16_t;
- typedef unsigned __int32 uint32_t;
- typedef unsigned __int64 uint64_t;
- typedef __int8 int8_t;
- typedef __int16 int16_t;
- typedef __int32 int32_t;
- typedef __int64 int64_t;
-#else
-# if defined(__GNU_LIBRARY__) && defined(__WORDSIZE) && (__WORDSIZE == 64)
-# define FMT64 "%l"
-# else
-# define FMT64 "%ll"
-# endif
-# ifndef __UD_STANDALONE__
-# include <inttypes.h>
-# endif /* __UD_STANDALONE__ */
-#endif
</del><span class="cx">
</span><span class="cx"> /* -----------------------------------------------------------------------------
</span><span class="cx"> * All possible "types" of objects in udis86. Order is Important!
</span><span class="lines">@@ -67,152 +61,176 @@
</span><span class="cx"> UD_NONE,
</span><span class="cx">
</span><span class="cx"> /* 8 bit GPRs */
</span><del>- UD_R_AL, UD_R_CL, UD_R_DL, UD_R_BL,
- UD_R_AH, UD_R_CH, UD_R_DH, UD_R_BH,
- UD_R_SPL, UD_R_BPL, UD_R_SIL, UD_R_DIL,
- UD_R_R8B, UD_R_R9B, UD_R_R10B, UD_R_R11B,
- UD_R_R12B, UD_R_R13B, UD_R_R14B, UD_R_R15B,
</del><ins>+ UD_R_AL, UD_R_CL, UD_R_DL, UD_R_BL,
+ UD_R_AH, UD_R_CH, UD_R_DH, UD_R_BH,
+ UD_R_SPL, UD_R_BPL, UD_R_SIL, UD_R_DIL,
+ UD_R_R8B, UD_R_R9B, UD_R_R10B, UD_R_R11B,
+ UD_R_R12B, UD_R_R13B, UD_R_R14B, UD_R_R15B,
</ins><span class="cx">
</span><span class="cx"> /* 16 bit GPRs */
</span><del>- UD_R_AX, UD_R_CX, UD_R_DX, UD_R_BX,
- UD_R_SP, UD_R_BP, UD_R_SI, UD_R_DI,
- UD_R_R8W, UD_R_R9W, UD_R_R10W, UD_R_R11W,
- UD_R_R12W, UD_R_R13W, UD_R_R14W, UD_R_R15W,
-
</del><ins>+ UD_R_AX, UD_R_CX, UD_R_DX, UD_R_BX,
+ UD_R_SP, UD_R_BP, UD_R_SI, UD_R_DI,
+ UD_R_R8W, UD_R_R9W, UD_R_R10W, UD_R_R11W,
+ UD_R_R12W, UD_R_R13W, UD_R_R14W, UD_R_R15W,
+
</ins><span class="cx"> /* 32 bit GPRs */
</span><del>- UD_R_EAX, UD_R_ECX, UD_R_EDX, UD_R_EBX,
- UD_R_ESP, UD_R_EBP, UD_R_ESI, UD_R_EDI,
- UD_R_R8D, UD_R_R9D, UD_R_R10D, UD_R_R11D,
- UD_R_R12D, UD_R_R13D, UD_R_R14D, UD_R_R15D,
-
</del><ins>+ UD_R_EAX, UD_R_ECX, UD_R_EDX, UD_R_EBX,
+ UD_R_ESP, UD_R_EBP, UD_R_ESI, UD_R_EDI,
+ UD_R_R8D, UD_R_R9D, UD_R_R10D, UD_R_R11D,
+ UD_R_R12D, UD_R_R13D, UD_R_R14D, UD_R_R15D,
+
</ins><span class="cx"> /* 64 bit GPRs */
</span><del>- UD_R_RAX, UD_R_RCX, UD_R_RDX, UD_R_RBX,
- UD_R_RSP, UD_R_RBP, UD_R_RSI, UD_R_RDI,
- UD_R_R8, UD_R_R9, UD_R_R10, UD_R_R11,
- UD_R_R12, UD_R_R13, UD_R_R14, UD_R_R15,
</del><ins>+ UD_R_RAX, UD_R_RCX, UD_R_RDX, UD_R_RBX,
+ UD_R_RSP, UD_R_RBP, UD_R_RSI, UD_R_RDI,
+ UD_R_R8, UD_R_R9, UD_R_R10, UD_R_R11,
+ UD_R_R12, UD_R_R13, UD_R_R14, UD_R_R15,
</ins><span class="cx">
</span><span class="cx"> /* segment registers */
</span><del>- UD_R_ES, UD_R_CS, UD_R_SS, UD_R_DS,
- UD_R_FS, UD_R_GS,
</del><ins>+ UD_R_ES, UD_R_CS, UD_R_SS, UD_R_DS,
+ UD_R_FS, UD_R_GS,
</ins><span class="cx">
</span><span class="cx"> /* control registers*/
</span><del>- UD_R_CR0, UD_R_CR1, UD_R_CR2, UD_R_CR3,
- UD_R_CR4, UD_R_CR5, UD_R_CR6, UD_R_CR7,
- UD_R_CR8, UD_R_CR9, UD_R_CR10, UD_R_CR11,
- UD_R_CR12, UD_R_CR13, UD_R_CR14, UD_R_CR15,
-
</del><ins>+ UD_R_CR0, UD_R_CR1, UD_R_CR2, UD_R_CR3,
+ UD_R_CR4, UD_R_CR5, UD_R_CR6, UD_R_CR7,
+ UD_R_CR8, UD_R_CR9, UD_R_CR10, UD_R_CR11,
+ UD_R_CR12, UD_R_CR13, UD_R_CR14, UD_R_CR15,
+
</ins><span class="cx"> /* debug registers */
</span><del>- UD_R_DR0, UD_R_DR1, UD_R_DR2, UD_R_DR3,
- UD_R_DR4, UD_R_DR5, UD_R_DR6, UD_R_DR7,
- UD_R_DR8, UD_R_DR9, UD_R_DR10, UD_R_DR11,
- UD_R_DR12, UD_R_DR13, UD_R_DR14, UD_R_DR15,
</del><ins>+ UD_R_DR0, UD_R_DR1, UD_R_DR2, UD_R_DR3,
+ UD_R_DR4, UD_R_DR5, UD_R_DR6, UD_R_DR7,
+ UD_R_DR8, UD_R_DR9, UD_R_DR10, UD_R_DR11,
+ UD_R_DR12, UD_R_DR13, UD_R_DR14, UD_R_DR15,
</ins><span class="cx">
</span><span class="cx"> /* mmx registers */
</span><del>- UD_R_MM0, UD_R_MM1, UD_R_MM2, UD_R_MM3,
- UD_R_MM4, UD_R_MM5, UD_R_MM6, UD_R_MM7,
</del><ins>+ UD_R_MM0, UD_R_MM1, UD_R_MM2, UD_R_MM3,
+ UD_R_MM4, UD_R_MM5, UD_R_MM6, UD_R_MM7,
</ins><span class="cx">
</span><span class="cx"> /* x87 registers */
</span><del>- UD_R_ST0, UD_R_ST1, UD_R_ST2, UD_R_ST3,
- UD_R_ST4, UD_R_ST5, UD_R_ST6, UD_R_ST7,
</del><ins>+ UD_R_ST0, UD_R_ST1, UD_R_ST2, UD_R_ST3,
+ UD_R_ST4, UD_R_ST5, UD_R_ST6, UD_R_ST7,
</ins><span class="cx">
</span><span class="cx"> /* extended multimedia registers */
</span><del>- UD_R_XMM0, UD_R_XMM1, UD_R_XMM2, UD_R_XMM3,
- UD_R_XMM4, UD_R_XMM5, UD_R_XMM6, UD_R_XMM7,
- UD_R_XMM8, UD_R_XMM9, UD_R_XMM10, UD_R_XMM11,
- UD_R_XMM12, UD_R_XMM13, UD_R_XMM14, UD_R_XMM15,
</del><ins>+ UD_R_XMM0, UD_R_XMM1, UD_R_XMM2, UD_R_XMM3,
+ UD_R_XMM4, UD_R_XMM5, UD_R_XMM6, UD_R_XMM7,
+ UD_R_XMM8, UD_R_XMM9, UD_R_XMM10, UD_R_XMM11,
+ UD_R_XMM12, UD_R_XMM13, UD_R_XMM14, UD_R_XMM15,
</ins><span class="cx">
</span><ins>+ /* 256B multimedia registers */
+ UD_R_YMM0, UD_R_YMM1, UD_R_YMM2, UD_R_YMM3,
+ UD_R_YMM4, UD_R_YMM5, UD_R_YMM6, UD_R_YMM7,
+ UD_R_YMM8, UD_R_YMM9, UD_R_YMM10, UD_R_YMM11,
+ UD_R_YMM12, UD_R_YMM13, UD_R_YMM14, UD_R_YMM15,
+
</ins><span class="cx"> UD_R_RIP,
</span><span class="cx">
</span><span class="cx"> /* Operand Types */
</span><del>- UD_OP_REG, UD_OP_MEM, UD_OP_PTR, UD_OP_IMM,
- UD_OP_JIMM, UD_OP_CONST
</del><ins>+ UD_OP_REG, UD_OP_MEM, UD_OP_PTR, UD_OP_IMM,
+ UD_OP_JIMM, UD_OP_CONST
</ins><span class="cx"> };
</span><span class="cx">
</span><span class="cx"> #include "udis86_itab.h"
</span><span class="cx">
</span><ins>+union ud_lval {
+ int8_t sbyte;
+ uint8_t ubyte;
+ int16_t sword;
+ uint16_t uword;
+ int32_t sdword;
+ uint32_t udword;
+ int64_t sqword;
+ uint64_t uqword;
+ struct {
+ uint16_t seg;
+ uint32_t off;
+ } ptr;
+};
+
</ins><span class="cx"> /* -----------------------------------------------------------------------------
</span><span class="cx"> * struct ud_operand - Disassembled instruction Operand.
</span><span class="cx"> * -----------------------------------------------------------------------------
</span><span class="cx"> */
</span><del>-struct ud_operand
-{
- enum ud_type type;
- uint8_t size;
- union {
- int8_t sbyte;
- uint8_t ubyte;
- int16_t sword;
- uint16_t uword;
- int32_t sdword;
- uint32_t udword;
- int64_t sqword;
- uint64_t uqword;
-
- struct {
- uint16_t seg;
- uint32_t off;
- } ptr;
- } lval;
-
- enum ud_type base;
- enum ud_type index;
- uint8_t offset;
- uint8_t scale;
</del><ins>+struct ud_operand {
+ enum ud_type type;
+ uint16_t size;
+ enum ud_type base;
+ enum ud_type index;
+ uint8_t scale;
+ uint8_t offset;
+ union ud_lval lval;
+ /*
+ * internal use only
+ */
+ uint64_t _legacy; /* this will be removed in 1.8 */
+ uint8_t _oprcode;
</ins><span class="cx"> };
</span><span class="cx">
</span><del>-#define UD_STRING_BUFFER_SIZE 64
-
</del><span class="cx"> /* -----------------------------------------------------------------------------
</span><span class="cx"> * struct ud - The udis86 object.
</span><span class="cx"> * -----------------------------------------------------------------------------
</span><span class="cx"> */
</span><span class="cx"> struct ud
</span><span class="cx"> {
</span><del>- int (*inp_hook) (struct ud*);
- uint8_t inp_curr;
- uint8_t inp_fill;
</del><ins>+ /*
+ * input buffering
+ */
+ int (*inp_hook) (struct ud*);
</ins><span class="cx"> #ifndef __UD_STANDALONE__
</span><del>- FILE* inp_file;
</del><ins>+ FILE* inp_file;
</ins><span class="cx"> #endif
</span><del>- uint8_t inp_ctr;
- uint8_t* inp_buff;
- uint8_t* inp_buff_end;
- uint8_t inp_end;
- void (*translator)(struct ud*);
- uint64_t insn_offset;
- char insn_hexcode[32];
- char insn_buffer[UD_STRING_BUFFER_SIZE];
- unsigned int insn_fill;
- uint8_t dis_mode;
- uint64_t pc;
- uint8_t vendor;
- struct map_entry* mapen;
- enum ud_mnemonic_code mnemonic;
- struct ud_operand operand[3];
- uint8_t error;
- uint8_t pfx_rex;
- uint8_t pfx_seg;
- uint8_t pfx_opr;
- uint8_t pfx_adr;
- uint8_t pfx_lock;
- uint8_t pfx_rep;
- uint8_t pfx_repe;
- uint8_t pfx_repne;
- uint8_t pfx_insn;
- uint8_t default64;
- uint8_t opr_mode;
- uint8_t adr_mode;
- uint8_t br_far;
- uint8_t br_near;
- uint8_t implicit_addr;
- uint8_t c1;
- uint8_t c2;
- uint8_t c3;
- uint8_t inp_cache[256];
- uint8_t inp_sess[64];
- uint8_t have_modrm;
- uint8_t modrm;
- void * user_opaque_data;
</del><ins>+ const uint8_t* inp_buf;
+ size_t inp_buf_size;
+ size_t inp_buf_index;
+ uint8_t inp_curr;
+ size_t inp_ctr;
+ uint8_t inp_sess[64];
+ int inp_end;
+ int inp_peek;
+
+ void (*translator)(struct ud*);
+ uint64_t insn_offset;
+ char insn_hexcode[64];
+
+ /*
+ * Assembly output buffer
+ */
+ char *asm_buf;
+ size_t asm_buf_size;
+ size_t asm_buf_fill;
+ char asm_buf_int[128];
+
+ /*
+ * Symbol resolver for use in the translation phase.
+ */
+ const char* (*sym_resolver)(struct ud*, uint64_t addr, int64_t *offset);
+
+ uint8_t dis_mode;
+ uint64_t pc;
+ uint8_t vendor;
+ enum ud_mnemonic_code mnemonic;
+ struct ud_operand operand[4];
+ uint8_t error;
+ uint8_t _rex;
+ uint8_t pfx_rex;
+ uint8_t pfx_seg;
+ uint8_t pfx_opr;
+ uint8_t pfx_adr;
+ uint8_t pfx_lock;
+ uint8_t pfx_str;
+ uint8_t pfx_rep;
+ uint8_t pfx_repe;
+ uint8_t pfx_repne;
+ uint8_t opr_mode;
+ uint8_t adr_mode;
+ uint8_t br_far;
+ uint8_t br_near;
+ uint8_t have_modrm;
+ uint8_t modrm;
+ uint8_t modrm_offset;
+ uint8_t vex_op;
+ uint8_t vex_b1;
+ uint8_t vex_b2;
+ uint8_t primary_opcode;
+ void * user_opaque_data;
</ins><span class="cx"> struct ud_itab_entry * itab_entry;
</span><span class="cx"> struct ud_lookup_table_list_entry *le;
</span><span class="cx"> };
</span><span class="lines">@@ -221,22 +239,22 @@
</span><span class="cx"> * Type-definitions
</span><span class="cx"> * -----------------------------------------------------------------------------
</span><span class="cx"> */
</span><del>-typedef enum ud_type ud_type_t;
-typedef enum ud_mnemonic_code ud_mnemonic_code_t;
</del><ins>+typedef enum ud_type ud_type_t;
+typedef enum ud_mnemonic_code ud_mnemonic_code_t;
</ins><span class="cx">
</span><del>-typedef struct ud ud_t;
-typedef struct ud_operand ud_operand_t;
</del><ins>+typedef struct ud ud_t;
+typedef struct ud_operand ud_operand_t;
</ins><span class="cx">
</span><del>-#define UD_SYN_INTEL ud_translate_intel
-#define UD_SYN_ATT ud_translate_att
-#define UD_EOI -1
-#define UD_INP_CACHE_SZ 32
-#define UD_VENDOR_AMD 0
-#define UD_VENDOR_INTEL 1
-#define UD_VENDOR_ANY 2
</del><ins>+#define UD_SYN_INTEL ud_translate_intel
+#define UD_SYN_ATT ud_translate_att
+#define UD_EOI (-1)
+#define UD_INP_CACHE_SZ 32
+#define UD_VENDOR_AMD 0
+#define UD_VENDOR_INTEL 1
+#define UD_VENDOR_ANY 2
</ins><span class="cx">
</span><del>-#define bail_out(ud,error_code) longjmp( (ud)->bailout, error_code )
-#define try_decode(ud) if ( setjmp( (ud)->bailout ) == 0 )
-#define catch_error() else
</del><ins>+#endif
</ins><span class="cx">
</span><del>-#endif
</del><ins>+/*
+vim: set ts=2 sw=2 expandtab
+*/
</ins></span></pre></div>
<a id="trunkSourceJavaScriptCoredisassemblerudis86udis86_udinthfromrev198831trunkSourceJavaScriptCoredisassemblerudis86udis86_externh"></a>
<div class="copfile"><h4>Copied: trunk/Source/JavaScriptCore/disassembler/udis86/udis86_udint.h (from rev 198831, trunk/Source/JavaScriptCore/disassembler/udis86/udis86_extern.h) (0 => 198832)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/disassembler/udis86/udis86_udint.h (rev 0)
+++ trunk/Source/JavaScriptCore/disassembler/udis86/udis86_udint.h 2016-03-30 07:17:14 UTC (rev 198832)
</span><span class="lines">@@ -0,0 +1,98 @@
</span><ins>+/* udis86 - libudis86/udint.h -- definitions for internal use only
+ *
+ * Copyright (c) 2002-2009 Vivek Thampi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _UDINT_H_
+#define _UDINT_H_
+
+#include "udis86_types.h"
+
+#ifdef HAVE_CONFIG_H
+# include <config.h>
+#endif /* HAVE_CONFIG_H */
+
+#if defined(UD_DEBUG) && HAVE_ASSERT_H
+# define UD_ASSERT(_x) ASSERT(_x)
+#else
+# define UD_ASSERT(_x)
+#endif /* !HAVE_ASSERT_H */
+
+#if defined(UD_DEBUG)
+ #define UDERR(u, msg) \
+ do { \
+ (u)->error = 1; \
+ fprintf(stderr, "decode-error: %s:%d: %s", \
+ __FILE__, __LINE__, (msg)); \
+ } while (0)
+#else
+ #define UDERR(u, m) \
+ do { \
+ (u)->error = 1; \
+ } while (0)
+#endif /* !LOGERR */
+
+#define UD_RETURN_ON_ERROR(u) \
+ do { \
+ if ((u)->error != 0) { \
+ return (u)->error; \
+ } \
+ } while (0)
+
+#define UD_RETURN_WITH_ERROR(u, m) \
+ do { \
+ UDERR(u, m); \
+ return (u)->error; \
+ } while (0)
+
+#ifndef __UD_STANDALONE__
+# define UD_NON_STANDALONE(x) x
+#else
+# define UD_NON_STANDALONE(x)
+#endif
+
+/* printf formatting int64 specifier */
+#ifdef FMT64
+# undef FMT64
+#endif
+#if defined(_MSC_VER) || defined(__BORLANDC__)
+# define FMT64 "I64"
+#else
+# if defined(__APPLE__)
+# define FMT64 "ll"
+# elif defined(__amd64__) || defined(__x86_64__)
+# define FMT64 "l"
+# else
+# define FMT64 "ll"
+# endif /* !x64 */
+#endif
+
+/* define an inline macro */
+#if defined(_MSC_VER) || defined(__BORLANDC__)
+# define UD_INLINE __inline /* MS Visual Studio requires __inline
+ instead of inline for C code */
+#else
+# define UD_INLINE inline
+#endif
+
+#endif /* _UDINT_H_ */
</ins></span></pre>
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