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<title>[194833] trunk/Source/JavaScriptCore</title>
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<dt>Revision</dt> <dd><a href="http://trac.webkit.org/projects/webkit/changeset/194833">194833</a></dd>
<dt>Author</dt> <dd>commit-queue@webkit.org</dd>
<dt>Date</dt> <dd>2016-01-10 14:33:01 -0800 (Sun, 10 Jan 2016)</dd>
</dl>
<h3>Log Message</h3>
<pre>[JSC] Make branchMul functional in ARM B3 and minor fixes
https://bugs.webkit.org/show_bug.cgi?id=152889
Patch by Benjamin Poulain <bpoulain@apple.com> on 2016-01-10
Reviewed by Mark Lam.
ARM64 does not have a "S" version of MUL setting the flags.
What we do is abstract that in the MacroAssembler. The problem
is that form requires scratch registers.
For simplicity, I just exposed the two scratch registers
for Air. Filip already added the concept of Scratch role,
all I needed was to expose it for opcodes.
* assembler/MacroAssemblerARM64.h:
(JSC::MacroAssemblerARM64::branchMul32):
(JSC::MacroAssemblerARM64::branchMul64):
Expose a version with the scratch registers as arguments.
* b3/B3LowerToAir.cpp:
(JSC::B3::Air::LowerToAir::lower):
Add the new form of CheckMul lowering.
* b3/air/AirOpcode.opcodes:
Expose the new BranchMuls.
Remove all the Test variants that use immediates
since Air can't handle those immediates correctly yet.
* b3/air/opcode_generator.rb:
Expose the Scratch role.
* b3/testb3.cpp:
(JSC::B3::testPatchpointLotsOfLateAnys):
Ooops, the scratch registers were not clobbered. We were just lucky
on x86.</pre>
<h3>Modified Paths</h3>
<ul>
<li><a href="#trunkSourceJavaScriptCoreChangeLog">trunk/Source/JavaScriptCore/ChangeLog</a></li>
<li><a href="#trunkSourceJavaScriptCoreassemblerMacroAssemblerARM64h">trunk/Source/JavaScriptCore/assembler/MacroAssemblerARM64.h</a></li>
<li><a href="#trunkSourceJavaScriptCoreb3B3LowerToAircpp">trunk/Source/JavaScriptCore/b3/B3LowerToAir.cpp</a></li>
<li><a href="#trunkSourceJavaScriptCoreb3airAirOpcodeopcodes">trunk/Source/JavaScriptCore/b3/air/AirOpcode.opcodes</a></li>
<li><a href="#trunkSourceJavaScriptCoreb3airopcode_generatorrb">trunk/Source/JavaScriptCore/b3/air/opcode_generator.rb</a></li>
<li><a href="#trunkSourceJavaScriptCoreb3testb3cpp">trunk/Source/JavaScriptCore/b3/testb3.cpp</a></li>
</ul>
</div>
<div id="patch">
<h3>Diff</h3>
<a id="trunkSourceJavaScriptCoreChangeLog"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/ChangeLog (194832 => 194833)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/ChangeLog 2016-01-10 21:56:07 UTC (rev 194832)
+++ trunk/Source/JavaScriptCore/ChangeLog 2016-01-10 22:33:01 UTC (rev 194833)
</span><span class="lines">@@ -1,5 +1,42 @@
</span><span class="cx"> 2016-01-10 Benjamin Poulain <bpoulain@apple.com>
</span><span class="cx">
</span><ins>+ [JSC] Make branchMul functional in ARM B3 and minor fixes
+ https://bugs.webkit.org/show_bug.cgi?id=152889
+
+ Reviewed by Mark Lam.
+
+ ARM64 does not have a "S" version of MUL setting the flags.
+ What we do is abstract that in the MacroAssembler. The problem
+ is that form requires scratch registers.
+
+ For simplicity, I just exposed the two scratch registers
+ for Air. Filip already added the concept of Scratch role,
+ all I needed was to expose it for opcodes.
+
+ * assembler/MacroAssemblerARM64.h:
+ (JSC::MacroAssemblerARM64::branchMul32):
+ (JSC::MacroAssemblerARM64::branchMul64):
+ Expose a version with the scratch registers as arguments.
+
+ * b3/B3LowerToAir.cpp:
+ (JSC::B3::Air::LowerToAir::lower):
+ Add the new form of CheckMul lowering.
+
+ * b3/air/AirOpcode.opcodes:
+ Expose the new BranchMuls.
+ Remove all the Test variants that use immediates
+ since Air can't handle those immediates correctly yet.
+
+ * b3/air/opcode_generator.rb:
+ Expose the Scratch role.
+
+ * b3/testb3.cpp:
+ (JSC::B3::testPatchpointLotsOfLateAnys):
+ Ooops, the scratch registers were not clobbered. We were just lucky
+ on x86.
+
+2016-01-10 Benjamin Poulain <bpoulain@apple.com>
+
</ins><span class="cx"> [JSC] B3 is unable to do function calls on ARM64
</span><span class="cx"> https://bugs.webkit.org/show_bug.cgi?id=152895
</span><span class="cx">
</span></span></pre></div>
<a id="trunkSourceJavaScriptCoreassemblerMacroAssemblerARM64h"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/assembler/MacroAssemblerARM64.h (194832 => 194833)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/assembler/MacroAssemblerARM64.h 2016-01-10 21:56:07 UTC (rev 194832)
+++ trunk/Source/JavaScriptCore/assembler/MacroAssemblerARM64.h 2016-01-10 22:33:01 UTC (rev 194833)
</span><span class="lines">@@ -2274,7 +2274,7 @@
</span><span class="cx"> return branchAdd64(cond, dest, imm, dest);
</span><span class="cx"> }
</span><span class="cx">
</span><del>- Jump branchMul32(ResultCondition cond, RegisterID src1, RegisterID src2, RegisterID dest)
</del><ins>+ Jump branchMul32(ResultCondition cond, RegisterID src1, RegisterID src2, RegisterID scratch1, RegisterID scratch2, RegisterID dest)
</ins><span class="cx"> {
</span><span class="cx"> ASSERT(cond != Signed);
</span><span class="cx">
</span><span class="lines">@@ -2285,16 +2285,21 @@
</span><span class="cx">
</span><span class="cx"> // This is a signed multiple of two 32-bit values, producing a 64-bit result.
</span><span class="cx"> m_assembler.smull(dest, src1, src2);
</span><del>- // Copy bits 63..32 of the result to bits 31..0 of dataTempRegister.
- m_assembler.asr<64>(getCachedDataTempRegisterIDAndInvalidate(), dest, 32);
- // Splat bit 31 of the result to bits 31..0 of memoryTempRegister.
- m_assembler.asr<32>(getCachedMemoryTempRegisterIDAndInvalidate(), dest, 31);
</del><ins>+ // Copy bits 63..32 of the result to bits 31..0 of scratch1.
+ m_assembler.asr<64>(scratch1, dest, 32);
+ // Splat bit 31 of the result to bits 31..0 of scratch2.
+ m_assembler.asr<32>(scratch2, dest, 31);
</ins><span class="cx"> // After a mul32 the top 32 bits of the register should be clear.
</span><span class="cx"> zeroExtend32ToPtr(dest, dest);
</span><span class="cx"> // Check that bits 31..63 of the original result were all equal.
</span><del>- return branch32(NotEqual, memoryTempRegister, dataTempRegister);
</del><ins>+ return branch32(NotEqual, scratch2, scratch1);
</ins><span class="cx"> }
</span><span class="cx">
</span><ins>+ Jump branchMul32(ResultCondition cond, RegisterID src1, RegisterID src2, RegisterID dest)
+ {
+ return branchMul32(cond, src1, src2, getCachedDataTempRegisterIDAndInvalidate(), getCachedMemoryTempRegisterIDAndInvalidate(), dest);
+ }
+
</ins><span class="cx"> Jump branchMul32(ResultCondition cond, RegisterID src, RegisterID dest)
</span><span class="cx"> {
</span><span class="cx"> return branchMul32(cond, dest, src, dest);
</span><span class="lines">@@ -2306,7 +2311,7 @@
</span><span class="cx"> return branchMul32(cond, dataTempRegister, src, dest);
</span><span class="cx"> }
</span><span class="cx">
</span><del>- Jump branchMul64(ResultCondition cond, RegisterID src1, RegisterID src2, RegisterID dest)
</del><ins>+ Jump branchMul64(ResultCondition cond, RegisterID src1, RegisterID src2, RegisterID scratch1, RegisterID scratch2, RegisterID dest)
</ins><span class="cx"> {
</span><span class="cx"> ASSERT(cond != Signed);
</span><span class="cx">
</span><span class="lines">@@ -2316,14 +2321,19 @@
</span><span class="cx"> if (cond != Overflow)
</span><span class="cx"> return branchTest64(cond, dest);
</span><span class="cx">
</span><del>- // Compute bits 127..64 of the result into dataTempRegister.
- m_assembler.smulh(getCachedDataTempRegisterIDAndInvalidate(), src1, src2);
- // Splat bit 63 of the result to bits 63..0 of memoryTempRegister.
- m_assembler.asr<64>(getCachedMemoryTempRegisterIDAndInvalidate(), dest, 63);
</del><ins>+ // Compute bits 127..64 of the result into scratch1.
+ m_assembler.smulh(scratch1, src1, src2);
+ // Splat bit 63 of the result to bits 63..0 of scratch2.
+ m_assembler.asr<64>(scratch2, dest, 63);
</ins><span class="cx"> // Check that bits 31..63 of the original result were all equal.
</span><del>- return branch64(NotEqual, memoryTempRegister, dataTempRegister);
</del><ins>+ return branch64(NotEqual, scratch2, scratch1);
</ins><span class="cx"> }
</span><span class="cx">
</span><ins>+ Jump branchMul64(ResultCondition cond, RegisterID src1, RegisterID src2, RegisterID dest)
+ {
+ return branchMul64(cond, src1, src2, getCachedDataTempRegisterIDAndInvalidate(), getCachedMemoryTempRegisterIDAndInvalidate(), dest);
+ }
+
</ins><span class="cx"> Jump branchMul64(ResultCondition cond, RegisterID src, RegisterID dest)
</span><span class="cx"> {
</span><span class="cx"> return branchMul64(cond, dest, src, dest);
</span></span></pre></div>
<a id="trunkSourceJavaScriptCoreb3B3LowerToAircpp"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/b3/B3LowerToAir.cpp (194832 => 194833)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/b3/B3LowerToAir.cpp 2016-01-10 21:56:07 UTC (rev 194832)
+++ trunk/Source/JavaScriptCore/b3/B3LowerToAir.cpp 2016-01-10 22:33:01 UTC (rev 194833)
</span><span class="lines">@@ -2091,12 +2091,19 @@
</span><span class="cx"> } else if (imm(right) && isValidForm(opcode, Arg::ResCond, Arg::Imm, Arg::Tmp)) {
</span><span class="cx"> sources.append(imm(right));
</span><span class="cx"> append(Move, tmp(left), result);
</span><del>- } else if (commutativity == Commutative && preferRightForResult(left, right)) {
</del><ins>+ } else if (isValidForm(opcode, Arg::ResCond, Arg::Tmp, Arg::Tmp)) {
+ if (commutativity == Commutative && preferRightForResult(left, right)) {
+ sources.append(tmp(left));
+ append(Move, tmp(right), result);
+ } else {
+ sources.append(tmp(right));
+ append(Move, tmp(left), result);
+ }
+ } else if (isValidForm(opcode, Arg::ResCond, Arg::Tmp, Arg::Tmp, Arg::Tmp, Arg::Tmp, Arg::Tmp)) {
</ins><span class="cx"> sources.append(tmp(left));
</span><del>- append(Move, tmp(right), result);
- } else {
</del><span class="cx"> sources.append(tmp(right));
</span><del>- append(Move, tmp(left), result);
</del><ins>+ sources.append(m_code.newTmp(Arg::typeForB3Type(m_value->type())));
+ sources.append(m_code.newTmp(Arg::typeForB3Type(m_value->type())));
</ins><span class="cx"> }
</span><span class="cx">
</span><span class="cx"> // There is a really hilarious case that arises when we do BranchAdd32(%x, %x). We won't emit
</span></span></pre></div>
<a id="trunkSourceJavaScriptCoreb3airAirOpcodeopcodes"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/b3/air/AirOpcode.opcodes (194832 => 194833)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/b3/air/AirOpcode.opcodes 2016-01-10 21:56:07 UTC (rev 194832)
+++ trunk/Source/JavaScriptCore/b3/air/AirOpcode.opcodes 2016-01-10 22:33:01 UTC (rev 194833)
</span><span class="lines">@@ -34,6 +34,7 @@
</span><span class="cx"> # U:F:64 => use of a double register or value
</span><span class="cx"> # D:F:32 => def of a float register or value
</span><span class="cx"> # UD:F:32 => use and def of a float register or value
</span><ins>+# S:F:32 => scratch float register.
</ins><span class="cx"> #
</span><span class="cx"> # Argument kinds:
</span><span class="cx"> # Tmp => temporary or register
</span><span class="lines">@@ -503,7 +504,7 @@
</span><span class="cx">
</span><span class="cx"> Compare32 U:G:32, U:G:32, U:G:32, ZD:G:32
</span><span class="cx"> RelCond, Tmp, Tmp, Tmp
</span><del>- RelCond, Tmp, Imm, Tmp
</del><ins>+ x86: RelCond, Tmp, Imm, Tmp
</ins><span class="cx">
</span><span class="cx"> 64: Compare64 U:G:32, U:G:64, U:G:64, ZD:G:32
</span><span class="cx"> RelCond, Tmp, Imm, Tmp
</span><span class="lines">@@ -552,7 +553,7 @@
</span><span class="cx">
</span><span class="cx"> BranchTest32 U:G:32, U:G:32, U:G:32 /branch
</span><span class="cx"> ResCond, Tmp, Tmp
</span><del>- ResCond, Tmp, Imm
</del><ins>+ x86: ResCond, Tmp, Imm
</ins><span class="cx"> x86: ResCond, Addr, Imm
</span><span class="cx"> x86: ResCond, Index, Imm
</span><span class="cx">
</span><span class="lines">@@ -560,7 +561,7 @@
</span><span class="cx"> # BranchTest32 in most cases where you use an immediate.
</span><span class="cx"> 64: BranchTest64 U:G:32, U:G:64, U:G:64 /branch
</span><span class="cx"> ResCond, Tmp, Tmp
</span><del>- ResCond, Tmp, Imm
</del><ins>+ x86: ResCond, Tmp, Imm
</ins><span class="cx"> x86: ResCond, Addr, Imm
</span><span class="cx"> x86: ResCond, Addr, Tmp
</span><span class="cx"> x86: ResCond, Index, Imm
</span><span class="lines">@@ -582,16 +583,22 @@
</span><span class="cx"> ResCond, Imm, Tmp
</span><span class="cx"> ResCond, Tmp, Tmp
</span><span class="cx">
</span><del>-BranchMul32 U:G:32, U:G:32, UZD:G:32 /branch
</del><ins>+x86: BranchMul32 U:G:32, U:G:32, UZD:G:32 /branch
</ins><span class="cx"> ResCond, Tmp, Tmp
</span><del>- x86: ResCond, Addr, Tmp
</del><ins>+ ResCond, Addr, Tmp
</ins><span class="cx">
</span><del>-BranchMul32 U:G:32, U:G:32, U:G:32, ZD:G:32 /branch
</del><ins>+x86: BranchMul32 U:G:32, U:G:32, U:G:32, ZD:G:32 /branch
</ins><span class="cx"> ResCond, Tmp, Imm, Tmp
</span><span class="cx">
</span><del>-64: BranchMul64 U:G:32, U:G:64, UZD:G:64 /branch
</del><ins>+arm64: BranchMul32 U:G:32, U:G:32, U:G:32, S:G:32, S:G:32, ZD:G:32 /branch
+ ResCond, Tmp, Tmp, Tmp, Tmp, Tmp
+
+x86_64: BranchMul64 U:G:32, U:G:64, UZD:G:64 /branch
</ins><span class="cx"> ResCond, Tmp, Tmp
</span><span class="cx">
</span><ins>+arm64: BranchMul64 U:G:32, U:G:64, U:G:64, S:G:64, S:G:64, ZD:G:64 /branch
+ ResCond, Tmp, Tmp, Tmp, Tmp, Tmp
+
</ins><span class="cx"> BranchSub32 U:G:32, U:G:32, UZD:G:32 /branch
</span><span class="cx"> ResCond, Tmp, Tmp
</span><span class="cx"> ResCond, Imm, Tmp
</span><span class="lines">@@ -637,7 +644,7 @@
</span><span class="cx">
</span><span class="cx"> MoveDoubleConditionallyTest32 U:G:32, U:G:32, U:G:32, U:F:64, UD:F:64
</span><span class="cx"> ResCond, Tmp, Tmp, Tmp, Tmp
</span><del>- ResCond, Tmp, Imm, Tmp, Tmp
</del><ins>+ x86: ResCond, Tmp, Imm, Tmp, Tmp
</ins><span class="cx">
</span><span class="cx"> 64: MoveDoubleConditionallyTest64 U:G:32, U:G:64, U:G:64, U:F:64, UD:F:64
</span><span class="cx"> ResCond, Tmp, Tmp, Tmp, Tmp
</span></span></pre></div>
<a id="trunkSourceJavaScriptCoreb3airopcode_generatorrb"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/b3/air/opcode_generator.rb (194832 => 194833)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/b3/air/opcode_generator.rb 2016-01-10 21:56:07 UTC (rev 194832)
+++ trunk/Source/JavaScriptCore/b3/air/opcode_generator.rb 2016-01-10 22:33:01 UTC (rev 194833)
</span><span class="lines">@@ -181,8 +181,8 @@
</span><span class="cx"> result
</span><span class="cx"> end
</span><span class="cx">
</span><del>-def isUD(token)
- token =~ /\A((U)|(D)|(UD)|(ZD)|(UZD)|(UA))\Z/
</del><ins>+def isRole(token)
+ token =~ /\A((U)|(D)|(UD)|(ZD)|(UZD)|(UA)|(S))\Z/
</ins><span class="cx"> end
</span><span class="cx">
</span><span class="cx"> def isGF(token)
</span><span class="lines">@@ -202,7 +202,7 @@
</span><span class="cx"> end
</span><span class="cx">
</span><span class="cx"> def isKeyword(token)
</span><del>- isUD(token) or isGF(token) or isKind(token) or isArch(token) or isWidth(token) or
</del><ins>+ isRole(token) or isGF(token) or isKind(token) or isArch(token) or isWidth(token) or
</ins><span class="cx"> token == "special" or token == "as"
</span><span class="cx"> end
</span><span class="cx">
</span><span class="lines">@@ -250,7 +250,7 @@
</span><span class="cx">
</span><span class="cx"> def consumeRole
</span><span class="cx"> result = token.string
</span><del>- parseError("Expected role (U, D, UD, or UA)") unless isUD(result)
</del><ins>+ parseError("Expected role (U, D, UD, ZD, UZD, UA, or S)") unless isRole(result)
</ins><span class="cx"> advance
</span><span class="cx"> result
</span><span class="cx"> end
</span><span class="lines">@@ -365,7 +365,7 @@
</span><span class="cx"> signature = []
</span><span class="cx"> forms = []
</span><span class="cx">
</span><del>- if isUD(token)
</del><ins>+ if isRole(token)
</ins><span class="cx"> loop {
</span><span class="cx"> role = consumeRole
</span><span class="cx"> consume(":")
</span><span class="lines">@@ -650,6 +650,8 @@
</span><span class="cx"> role = "UseZDef"
</span><span class="cx"> when "UA"
</span><span class="cx"> role = "UseAddr"
</span><ins>+ when "S"
+ role = "Scratch"
</ins><span class="cx"> else
</span><span class="cx"> raise
</span><span class="cx"> end
</span></span></pre></div>
<a id="trunkSourceJavaScriptCoreb3testb3cpp"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/b3/testb3.cpp (194832 => 194833)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/b3/testb3.cpp 2016-01-10 21:56:07 UTC (rev 194832)
+++ trunk/Source/JavaScriptCore/b3/testb3.cpp 2016-01-10 22:33:01 UTC (rev 194833)
</span><span class="lines">@@ -6240,6 +6240,7 @@
</span><span class="cx"> }
</span><span class="cx">
</span><span class="cx"> PatchpointValue* patchpoint = root->appendNew<PatchpointValue>(proc, Int32, Origin());
</span><ins>+ patchpoint->clobber(RegisterSet::macroScratchRegisters());
</ins><span class="cx"> for (Value* value : values)
</span><span class="cx"> patchpoint->append(ConstrainedValue(value, ValueRep::LateColdAny));
</span><span class="cx"> patchpoint->setGenerator(
</span></span></pre>
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