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<dl class="meta">
<dt>Revision</dt> <dd><a href="http://trac.webkit.org/projects/webkit/changeset/194663">194663</a></dd>
<dt>Author</dt> <dd>commit-queue@webkit.org</dd>
<dt>Date</dt> <dd>2016-01-06 13:37:29 -0800 (Wed, 06 Jan 2016)</dd>
</dl>
<h3>Log Message</h3>
<pre>[JSC] More B3 tests passing on ARM64
https://bugs.webkit.org/show_bug.cgi?id=152787
Patch by Benjamin Poulain <bpoulain@apple.com> on 2016-01-06
Reviewed by Michael Saboff.
Some more minor bugs.
* assembler/MacroAssemblerARM64.h:
(JSC::MacroAssemblerARM64::urshift64):
The offset was being truncated. That code was just copied
from the 32bits version of urshift.
* b3/B3LowerToAir.cpp:
(JSC::B3::Air::LowerToAir::createGenericCompare):
Very few instructions can encode -1 as immediate.
TST certainly can't. The fallback works for ARM.
* b3/air/AirOpcode.opcodes:
Bit instructions have very specific immediate encoding.
B3 cannot express that properly yet. I disabled those
forms for now. Immediates encoding is something we'll really
have to look into at some point for B3 ARM64.</pre>
<h3>Modified Paths</h3>
<ul>
<li><a href="#trunkSourceJavaScriptCoreChangeLog">trunk/Source/JavaScriptCore/ChangeLog</a></li>
<li><a href="#trunkSourceJavaScriptCoreassemblerMacroAssemblerARM64h">trunk/Source/JavaScriptCore/assembler/MacroAssemblerARM64.h</a></li>
<li><a href="#trunkSourceJavaScriptCoreb3B3LowerToAircpp">trunk/Source/JavaScriptCore/b3/B3LowerToAir.cpp</a></li>
<li><a href="#trunkSourceJavaScriptCoreb3airAirOpcodeopcodes">trunk/Source/JavaScriptCore/b3/air/AirOpcode.opcodes</a></li>
</ul>
</div>
<div id="patch">
<h3>Diff</h3>
<a id="trunkSourceJavaScriptCoreChangeLog"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/ChangeLog (194662 => 194663)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/ChangeLog 2016-01-06 21:32:59 UTC (rev 194662)
+++ trunk/Source/JavaScriptCore/ChangeLog 2016-01-06 21:37:29 UTC (rev 194663)
</span><span class="lines">@@ -1,3 +1,28 @@
</span><ins>+2016-01-06 Benjamin Poulain <bpoulain@apple.com>
+
+ [JSC] More B3 tests passing on ARM64
+ https://bugs.webkit.org/show_bug.cgi?id=152787
+
+ Reviewed by Michael Saboff.
+
+ Some more minor bugs.
+
+ * assembler/MacroAssemblerARM64.h:
+ (JSC::MacroAssemblerARM64::urshift64):
+ The offset was being truncated. That code was just copied
+ from the 32bits version of urshift.
+
+ * b3/B3LowerToAir.cpp:
+ (JSC::B3::Air::LowerToAir::createGenericCompare):
+ Very few instructions can encode -1 as immediate.
+ TST certainly can't. The fallback works for ARM.
+
+ * b3/air/AirOpcode.opcodes:
+ Bit instructions have very specific immediate encoding.
+ B3 cannot express that properly yet. I disabled those
+ forms for now. Immediates encoding is something we'll really
+ have to look into at some point for B3 ARM64.
+
</ins><span class="cx"> 2016-01-06 Michael Catanzaro <mcatanzaro@igalia.com>
</span><span class="cx">
</span><span class="cx"> Silence -Wtautological-compare
</span></span></pre></div>
<a id="trunkSourceJavaScriptCoreassemblerMacroAssemblerARM64h"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/assembler/MacroAssemblerARM64.h (194662 => 194663)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/assembler/MacroAssemblerARM64.h 2016-01-06 21:32:59 UTC (rev 194662)
+++ trunk/Source/JavaScriptCore/assembler/MacroAssemblerARM64.h 2016-01-06 21:37:29 UTC (rev 194663)
</span><span class="lines">@@ -762,7 +762,7 @@
</span><span class="cx">
</span><span class="cx"> void urshift64(RegisterID src, TrustedImm32 imm, RegisterID dest)
</span><span class="cx"> {
</span><del>- m_assembler.lsr<64>(dest, src, imm.m_value & 0x1f);
</del><ins>+ m_assembler.lsr<64>(dest, src, imm.m_value & 0x3f);
</ins><span class="cx"> }
</span><span class="cx">
</span><span class="cx"> void urshift64(RegisterID shiftAmount, RegisterID dest)
</span></span></pre></div>
<a id="trunkSourceJavaScriptCoreb3B3LowerToAircpp"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/b3/B3LowerToAir.cpp (194662 => 194663)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/b3/B3LowerToAir.cpp 2016-01-06 21:32:59 UTC (rev 194662)
+++ trunk/Source/JavaScriptCore/b3/B3LowerToAir.cpp 2016-01-06 21:37:29 UTC (rev 194663)
</span><span class="lines">@@ -1267,37 +1267,39 @@
</span><span class="cx"> }
</span><span class="cx"> }
</span><span class="cx">
</span><del>- if (canCommitInternal && value->as<MemoryValue>()) {
- // Handle things like Branch(Load8Z(value))
</del><ins>+ if (Arg::isValidImmForm(-1)) {
+ if (canCommitInternal && value->as<MemoryValue>()) {
+ // Handle things like Branch(Load8Z(value))
</ins><span class="cx">
</span><del>- if (Inst result = tryTest(Arg::Width8, loadPromise(value, Load8Z), Arg::imm(-1))) {
- commitInternal(value);
- return result;
- }
</del><ins>+ if (Inst result = tryTest(Arg::Width8, loadPromise(value, Load8Z), Arg::imm(-1))) {
+ commitInternal(value);
+ return result;
+ }
</ins><span class="cx">
</span><del>- if (Inst result = tryTest(Arg::Width8, loadPromise(value, Load8S), Arg::imm(-1))) {
- commitInternal(value);
- return result;
- }
</del><ins>+ if (Inst result = tryTest(Arg::Width8, loadPromise(value, Load8S), Arg::imm(-1))) {
+ commitInternal(value);
+ return result;
+ }
</ins><span class="cx">
</span><del>- if (Inst result = tryTest(Arg::Width16, loadPromise(value, Load16Z), Arg::imm(-1))) {
- commitInternal(value);
- return result;
- }
</del><ins>+ if (Inst result = tryTest(Arg::Width16, loadPromise(value, Load16Z), Arg::imm(-1))) {
+ commitInternal(value);
+ return result;
+ }
</ins><span class="cx">
</span><del>- if (Inst result = tryTest(Arg::Width16, loadPromise(value, Load16S), Arg::imm(-1))) {
- commitInternal(value);
- return result;
</del><ins>+ if (Inst result = tryTest(Arg::Width16, loadPromise(value, Load16S), Arg::imm(-1))) {
+ commitInternal(value);
+ return result;
+ }
+
+ if (Inst result = tryTest(width, loadPromise(value), Arg::imm(-1))) {
+ commitInternal(value);
+ return result;
+ }
</ins><span class="cx"> }
</span><span class="cx">
</span><del>- if (Inst result = tryTest(width, loadPromise(value), Arg::imm(-1))) {
- commitInternal(value);
</del><ins>+ if (Inst result = test(width, resCond, tmpPromise(value), Arg::imm(-1)))
</ins><span class="cx"> return result;
</span><del>- }
</del><span class="cx"> }
</span><del>-
- if (Inst result = test(width, resCond, tmpPromise(value), Arg::imm(-1)))
- return result;
</del><span class="cx">
</span><span class="cx"> // Sometimes this is the only form of test available. We prefer not to use this because
</span><span class="cx"> // it's less canonical.
</span></span></pre></div>
<a id="trunkSourceJavaScriptCoreb3airAirOpcodeopcodes"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/b3/air/AirOpcode.opcodes (194662 => 194663)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/b3/air/AirOpcode.opcodes 2016-01-06 21:32:59 UTC (rev 194662)
+++ trunk/Source/JavaScriptCore/b3/air/AirOpcode.opcodes 2016-01-06 21:37:29 UTC (rev 194663)
</span><span class="lines">@@ -232,14 +232,14 @@
</span><span class="cx">
</span><span class="cx"> And32 U:G:32, UZD:G:32
</span><span class="cx"> Tmp, Tmp
</span><del>- Imm, Tmp
</del><ins>+ x86: Imm, Tmp
</ins><span class="cx"> x86: Tmp, Addr
</span><span class="cx"> x86: Addr, Tmp
</span><span class="cx"> x86: Imm, Addr
</span><span class="cx">
</span><span class="cx"> 64: And64 U:G:64, UD:G:64
</span><span class="cx"> Tmp, Tmp
</span><del>- Imm, Tmp
</del><ins>+ x86: Imm, Tmp
</ins><span class="cx">
</span><span class="cx"> arm64: AndDouble U:F:64, U:F:64, D:F:64
</span><span class="cx"> Tmp, Tmp, Tmp
</span><span class="lines">@@ -303,18 +303,18 @@
</span><span class="cx">
</span><span class="cx"> Or32 U:G:32, UZD:G:32
</span><span class="cx"> Tmp, Tmp
</span><del>- Imm, Tmp
</del><ins>+ x86: Imm, Tmp
</ins><span class="cx"> x86: Tmp, Addr
</span><span class="cx"> x86: Addr, Tmp
</span><span class="cx"> x86: Imm, Addr
</span><span class="cx">
</span><span class="cx"> 64: Or64 U:G:64, UD:G:64
</span><span class="cx"> Tmp, Tmp
</span><del>- Imm, Tmp
</del><ins>+ x86: Imm, Tmp
</ins><span class="cx">
</span><span class="cx"> Xor32 U:G:32, UZD:G:32
</span><span class="cx"> Tmp, Tmp
</span><del>- Imm, Tmp
</del><ins>+ x86: Imm, Tmp
</ins><span class="cx"> x86: Tmp, Addr
</span><span class="cx"> x86: Addr, Tmp
</span><span class="cx"> x86: Imm, Addr
</span><span class="lines">@@ -322,7 +322,7 @@
</span><span class="cx"> 64: Xor64 U:G:64, UD:G:64
</span><span class="cx"> Tmp, Tmp
</span><span class="cx"> x86: Tmp, Addr
</span><del>- Imm, Tmp
</del><ins>+ x86: Imm, Tmp
</ins><span class="cx">
</span><span class="cx"> arm64: Not32 U:G:32, ZD:G:32
</span><span class="cx"> Tmp, Tmp
</span></span></pre>
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