<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN"
"http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head><meta http-equiv="content-type" content="text/html; charset=utf-8" />
<title>[192355] trunk/Source/JavaScriptCore</title>
</head>
<body>
<style type="text/css"><!--
#msg dl.meta { border: 1px #006 solid; background: #369; padding: 6px; color: #fff; }
#msg dl.meta dt { float: left; width: 6em; font-weight: bold; }
#msg dt:after { content:':';}
#msg dl, #msg dt, #msg ul, #msg li, #header, #footer, #logmsg { font-family: verdana,arial,helvetica,sans-serif; font-size: 10pt; }
#msg dl a { font-weight: bold}
#msg dl a:link { color:#fc3; }
#msg dl a:active { color:#ff0; }
#msg dl a:visited { color:#cc6; }
h3 { font-family: verdana,arial,helvetica,sans-serif; font-size: 10pt; font-weight: bold; }
#msg pre { overflow: auto; background: #ffc; border: 1px #fa0 solid; padding: 6px; }
#logmsg { background: #ffc; border: 1px #fa0 solid; padding: 1em 1em 0 1em; }
#logmsg p, #logmsg pre, #logmsg blockquote { margin: 0 0 1em 0; }
#logmsg p, #logmsg li, #logmsg dt, #logmsg dd { line-height: 14pt; }
#logmsg h1, #logmsg h2, #logmsg h3, #logmsg h4, #logmsg h5, #logmsg h6 { margin: .5em 0; }
#logmsg h1:first-child, #logmsg h2:first-child, #logmsg h3:first-child, #logmsg h4:first-child, #logmsg h5:first-child, #logmsg h6:first-child { margin-top: 0; }
#logmsg ul, #logmsg ol { padding: 0; list-style-position: inside; margin: 0 0 0 1em; }
#logmsg ul { text-indent: -1em; padding-left: 1em; }#logmsg ol { text-indent: -1.5em; padding-left: 1.5em; }
#logmsg > ul, #logmsg > ol { margin: 0 0 1em 0; }
#logmsg pre { background: #eee; padding: 1em; }
#logmsg blockquote { border: 1px solid #fa0; border-left-width: 10px; padding: 1em 1em 0 1em; background: white;}
#logmsg dl { margin: 0; }
#logmsg dt { font-weight: bold; }
#logmsg dd { margin: 0; padding: 0 0 0.5em 0; }
#logmsg dd:before { content:'\00bb';}
#logmsg table { border-spacing: 0px; border-collapse: collapse; border-top: 4px solid #fa0; border-bottom: 1px solid #fa0; background: #fff; }
#logmsg table th { text-align: left; font-weight: normal; padding: 0.2em 0.5em; border-top: 1px dotted #fa0; }
#logmsg table td { text-align: right; border-top: 1px dotted #fa0; padding: 0.2em 0.5em; }
#logmsg table thead th { text-align: center; border-bottom: 1px solid #fa0; }
#logmsg table th.Corner { text-align: left; }
#logmsg hr { border: none 0; border-top: 2px dashed #fa0; height: 1px; }
#header, #footer { color: #fff; background: #636; border: 1px #300 solid; padding: 6px; }
#patch { width: 100%; }
#patch h4 {font-family: verdana,arial,helvetica,sans-serif;font-size:10pt;padding:8px;background:#369;color:#fff;margin:0;}
#patch .propset h4, #patch .binary h4 {margin:0;}
#patch pre {padding:0;line-height:1.2em;margin:0;}
#patch .diff {width:100%;background:#eee;padding: 0 0 10px 0;overflow:auto;}
#patch .propset .diff, #patch .binary .diff {padding:10px 0;}
#patch span {display:block;padding:0 10px;}
#patch .modfile, #patch .addfile, #patch .delfile, #patch .propset, #patch .binary, #patch .copfile {border:1px solid #ccc;margin:10px 0;}
#patch ins {background:#dfd;text-decoration:none;display:block;padding:0 10px;}
#patch del {background:#fdd;text-decoration:none;display:block;padding:0 10px;}
#patch .lines, .info {color:#888;background:#fff;}
--></style>
<div id="msg">
<dl class="meta">
<dt>Revision</dt> <dd><a href="http://trac.webkit.org/projects/webkit/changeset/192355">192355</a></dd>
<dt>Author</dt> <dd>benjamin@webkit.org</dd>
<dt>Date</dt> <dd>2015-11-11 23:38:00 -0800 (Wed, 11 Nov 2015)</dd>
</dl>
<h3>Log Message</h3>
<pre>[JSC] Air: we have more register than what the allocator believed
https://bugs.webkit.org/show_bug.cgi?id=151182
Patch by Benjamin Poulain <bpoulain@apple.com> on 2015-11-11
Reviewed by Michael Saboff.
I was using GPRInfo/FPRInfo to get the number of register while coloring the interference graph.
The problem is, those classes are lying about register availability.
They don't report stuff reserved by the MacroAssembler and reserve some registers.
FPRInfo is the worst, reporting only 6 of the 15 registers we have.
The ground truth in our case is that we can color with all the registers returned
by regsInPriorityOrder(). I changed IteratedRegisterCoalescingAllocator to use that value.
The new test testSpillFP() covers simple spilling of doubles.
* b3/air/AirIteratedRegisterCoalescing.cpp:
(JSC::B3::Air::IteratedRegisterCoalescingAllocator::IteratedRegisterCoalescingAllocator):
(JSC::B3::Air::IteratedRegisterCoalescingAllocator::makeWorkList):
(JSC::B3::Air::IteratedRegisterCoalescingAllocator::decrementDegree):
(JSC::B3::Air::IteratedRegisterCoalescingAllocator::precoloredCoalescingHeuristic):
(JSC::B3::Air::IteratedRegisterCoalescingAllocator::conservativeHeuristic):
(JSC::B3::Air::IteratedRegisterCoalescingAllocator::addWorkList):
(JSC::B3::Air::IteratedRegisterCoalescingAllocator::combine):
(JSC::B3::Air::IteratedRegisterCoalescingAllocator::freezeMoves):
* b3/testb3.cpp:
(JSC::B3::testSpillFP):
(JSC::B3::run):</pre>
<h3>Modified Paths</h3>
<ul>
<li><a href="#trunkSourceJavaScriptCoreChangeLog">trunk/Source/JavaScriptCore/ChangeLog</a></li>
<li><a href="#trunkSourceJavaScriptCoreb3airAirIteratedRegisterCoalescingcpp">trunk/Source/JavaScriptCore/b3/air/AirIteratedRegisterCoalescing.cpp</a></li>
<li><a href="#trunkSourceJavaScriptCoreb3testb3cpp">trunk/Source/JavaScriptCore/b3/testb3.cpp</a></li>
</ul>
</div>
<div id="patch">
<h3>Diff</h3>
<a id="trunkSourceJavaScriptCoreChangeLog"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/ChangeLog (192354 => 192355)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/ChangeLog 2015-11-12 07:28:57 UTC (rev 192354)
+++ trunk/Source/JavaScriptCore/ChangeLog 2015-11-12 07:38:00 UTC (rev 192355)
</span><span class="lines">@@ -1,3 +1,34 @@
</span><ins>+2015-11-11 Benjamin Poulain <bpoulain@apple.com>
+
+ [JSC] Air: we have more register than what the allocator believed
+ https://bugs.webkit.org/show_bug.cgi?id=151182
+
+ Reviewed by Michael Saboff.
+
+ I was using GPRInfo/FPRInfo to get the number of register while coloring the interference graph.
+ The problem is, those classes are lying about register availability.
+
+ They don't report stuff reserved by the MacroAssembler and reserve some registers.
+ FPRInfo is the worst, reporting only 6 of the 15 registers we have.
+
+ The ground truth in our case is that we can color with all the registers returned
+ by regsInPriorityOrder(). I changed IteratedRegisterCoalescingAllocator to use that value.
+
+ The new test testSpillFP() covers simple spilling of doubles.
+
+ * b3/air/AirIteratedRegisterCoalescing.cpp:
+ (JSC::B3::Air::IteratedRegisterCoalescingAllocator::IteratedRegisterCoalescingAllocator):
+ (JSC::B3::Air::IteratedRegisterCoalescingAllocator::makeWorkList):
+ (JSC::B3::Air::IteratedRegisterCoalescingAllocator::decrementDegree):
+ (JSC::B3::Air::IteratedRegisterCoalescingAllocator::precoloredCoalescingHeuristic):
+ (JSC::B3::Air::IteratedRegisterCoalescingAllocator::conservativeHeuristic):
+ (JSC::B3::Air::IteratedRegisterCoalescingAllocator::addWorkList):
+ (JSC::B3::Air::IteratedRegisterCoalescingAllocator::combine):
+ (JSC::B3::Air::IteratedRegisterCoalescingAllocator::freezeMoves):
+ * b3/testb3.cpp:
+ (JSC::B3::testSpillFP):
+ (JSC::B3::run):
+
</ins><span class="cx"> 2015-11-11 Mark Lam <mark.lam@apple.com>
</span><span class="cx">
</span><span class="cx"> The BinarySnippetRegisterContext needs to copy the result back from the scratch register.
</span></span></pre></div>
<a id="trunkSourceJavaScriptCoreb3airAirIteratedRegisterCoalescingcpp"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/b3/air/AirIteratedRegisterCoalescing.cpp (192354 => 192355)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/b3/air/AirIteratedRegisterCoalescing.cpp 2015-11-12 07:28:57 UTC (rev 192354)
+++ trunk/Source/JavaScriptCore/b3/air/AirIteratedRegisterCoalescing.cpp 2015-11-12 07:38:00 UTC (rev 192355)
</span><span class="lines">@@ -128,22 +128,10 @@
</span><span class="cx"> };
</span><span class="cx">
</span><span class="cx"> template<Arg::Type type>
</span><del>-struct Bank;
-
-template<>
-struct Bank<Arg::GP> {
- typedef GPRInfo Info;
-};
-
-template<>
-struct Bank<Arg::FP> {
- typedef FPRInfo Info;
-};
-
-template<Arg::Type type>
</del><span class="cx"> class IteratedRegisterCoalescingAllocator {
</span><span class="cx"> public:
</span><span class="cx"> IteratedRegisterCoalescingAllocator(Code& code)
</span><ins>+ : m_numberOfRegisters(regsInPriorityOrder(type).size())
</ins><span class="cx"> {
</span><span class="cx"> initializeDegrees(code);
</span><span class="cx">
</span><span class="lines">@@ -324,7 +312,7 @@
</span><span class="cx">
</span><span class="cx"> Tmp tmp = AbsoluteTmpHelper<type>::tmpFromAbsoluteIndex(i);
</span><span class="cx">
</span><del>- if (degree >= Bank<type>::Info::numberOfRegisters)
</del><ins>+ if (degree >= m_numberOfRegisters)
</ins><span class="cx"> m_spillWorklist.add(tmp);
</span><span class="cx"> else if (!m_moveList[AbsoluteTmpHelper<type>::absoluteIndex(tmp)].isEmpty())
</span><span class="cx"> m_freezeWorklist.add(tmp);
</span><span class="lines">@@ -366,7 +354,7 @@
</span><span class="cx"> ASSERT(m_degrees[AbsoluteTmpHelper<type>::absoluteIndex(tmp)]);
</span><span class="cx">
</span><span class="cx"> unsigned oldDegree = m_degrees[AbsoluteTmpHelper<type>::absoluteIndex(tmp)]--;
</span><del>- if (oldDegree == Bank<type>::Info::numberOfRegisters) {
</del><ins>+ if (oldDegree == m_numberOfRegisters) {
</ins><span class="cx"> enableMovesOnValueAndAdjacents(tmp);
</span><span class="cx"> m_spillWorklist.remove(tmp);
</span><span class="cx"> if (isMoveRelated(tmp))
</span><span class="lines">@@ -472,7 +460,7 @@
</span><span class="cx"> for (Tmp adjacentTmp : adjacentsOfV) {
</span><span class="cx"> if (!adjacentTmp.isReg()
</span><span class="cx"> && !hasBeenSimplified(adjacentTmp)
</span><del>- && m_degrees[AbsoluteTmpHelper<type>::absoluteIndex(adjacentTmp)] >= Bank<type>::Info::numberOfRegisters
</del><ins>+ && m_degrees[AbsoluteTmpHelper<type>::absoluteIndex(adjacentTmp)] >= m_numberOfRegisters
</ins><span class="cx"> && !m_interferenceEdges.contains(InterferenceEdge(u, adjacentTmp)))
</span><span class="cx"> return false;
</span><span class="cx"> }
</span><span class="lines">@@ -493,7 +481,7 @@
</span><span class="cx"> auto adjacentsOfU = m_adjacencyList[AbsoluteTmpHelper<type>::absoluteIndex(u)];
</span><span class="cx"> auto adjacentsOfV = m_adjacencyList[AbsoluteTmpHelper<type>::absoluteIndex(v)];
</span><span class="cx">
</span><del>- if (adjacentsOfU.size() + adjacentsOfV.size() < Bank<type>::Info::numberOfRegisters) {
</del><ins>+ if (adjacentsOfU.size() + adjacentsOfV.size() < m_numberOfRegisters) {
</ins><span class="cx"> // Shortcut: if the total number of adjacents is less than the number of register, the condition is always met.
</span><span class="cx"> return true;
</span><span class="cx"> }
</span><span class="lines">@@ -503,29 +491,29 @@
</span><span class="cx"> for (Tmp adjacentTmp : adjacentsOfU) {
</span><span class="cx"> ASSERT(adjacentTmp != v);
</span><span class="cx"> ASSERT(adjacentTmp != u);
</span><del>- if (!hasBeenSimplified(adjacentTmp) && m_degrees[AbsoluteTmpHelper<type>::absoluteIndex(adjacentTmp)] >= Bank<type>::Info::numberOfRegisters) {
</del><ins>+ if (!hasBeenSimplified(adjacentTmp) && m_degrees[AbsoluteTmpHelper<type>::absoluteIndex(adjacentTmp)] >= m_numberOfRegisters) {
</ins><span class="cx"> auto addResult = highOrderAdjacents.add(adjacentTmp);
</span><del>- if (addResult.isNewEntry && highOrderAdjacents.size() >= Bank<type>::Info::numberOfRegisters)
</del><ins>+ if (addResult.isNewEntry && highOrderAdjacents.size() >= m_numberOfRegisters)
</ins><span class="cx"> return false;
</span><span class="cx"> }
</span><span class="cx"> }
</span><span class="cx"> for (Tmp adjacentTmp : adjacentsOfV) {
</span><span class="cx"> ASSERT(adjacentTmp != u);
</span><span class="cx"> ASSERT(adjacentTmp != v);
</span><del>- if (!hasBeenSimplified(adjacentTmp) && m_degrees[AbsoluteTmpHelper<type>::absoluteIndex(adjacentTmp)] >= Bank<type>::Info::numberOfRegisters) {
</del><ins>+ if (!hasBeenSimplified(adjacentTmp) && m_degrees[AbsoluteTmpHelper<type>::absoluteIndex(adjacentTmp)] >= m_numberOfRegisters) {
</ins><span class="cx"> auto addResult = highOrderAdjacents.add(adjacentTmp);
</span><del>- if (addResult.isNewEntry && highOrderAdjacents.size() >= Bank<type>::Info::numberOfRegisters)
</del><ins>+ if (addResult.isNewEntry && highOrderAdjacents.size() >= m_numberOfRegisters)
</ins><span class="cx"> return false;
</span><span class="cx"> }
</span><span class="cx"> }
</span><span class="cx">
</span><del>- ASSERT(highOrderAdjacents.size() < Bank<type>::Info::numberOfRegisters);
</del><ins>+ ASSERT(highOrderAdjacents.size() < m_numberOfRegisters);
</ins><span class="cx"> return true;
</span><span class="cx"> }
</span><span class="cx">
</span><span class="cx"> void addWorkList(Tmp tmp)
</span><span class="cx"> {
</span><del>- if (!tmp.isReg() && m_degrees[AbsoluteTmpHelper<type>::absoluteIndex(tmp)] < Bank<type>::Info::numberOfRegisters && !isMoveRelated(tmp)) {
</del><ins>+ if (!tmp.isReg() && m_degrees[AbsoluteTmpHelper<type>::absoluteIndex(tmp)] < m_numberOfRegisters && !isMoveRelated(tmp)) {
</ins><span class="cx"> m_freezeWorklist.remove(tmp);
</span><span class="cx"> m_simplifyWorklist.append(tmp);
</span><span class="cx"> }
</span><span class="lines">@@ -547,7 +535,7 @@
</span><span class="cx"> decrementDegree(adjacentTmp);
</span><span class="cx"> });
</span><span class="cx">
</span><del>- if (m_degrees[AbsoluteTmpHelper<type>::absoluteIndex(u)] >= Bank<type>::Info::numberOfRegisters && m_freezeWorklist.remove(u))
</del><ins>+ if (m_degrees[AbsoluteTmpHelper<type>::absoluteIndex(u)] >= m_numberOfRegisters && m_freezeWorklist.remove(u))
</ins><span class="cx"> m_spillWorklist.add(u);
</span><span class="cx"> }
</span><span class="cx">
</span><span class="lines">@@ -565,7 +553,7 @@
</span><span class="cx"> m_worklistMoves.remove(&inst);
</span><span class="cx">
</span><span class="cx"> Tmp otherTmp = inst.args[0].tmp() != tmp ? inst.args[0].tmp() : inst.args[1].tmp();
</span><del>- if (m_degrees[AbsoluteTmpHelper<type>::absoluteIndex(otherTmp)] < Bank<type>::Info::numberOfRegisters && !isMoveRelated(otherTmp)) {
</del><ins>+ if (m_degrees[AbsoluteTmpHelper<type>::absoluteIndex(otherTmp)] < m_numberOfRegisters && !isMoveRelated(otherTmp)) {
</ins><span class="cx"> m_freezeWorklist.remove(otherTmp);
</span><span class="cx"> m_simplifyWorklist.append(otherTmp);
</span><span class="cx"> }
</span><span class="lines">@@ -754,6 +742,8 @@
</span><span class="cx"> };
</span><span class="cx"> typedef SimpleClassHashTraits<InterferenceEdge> InterferenceEdgeHashTraits;
</span><span class="cx">
</span><ins>+ unsigned m_numberOfRegisters { 0 };
+
</ins><span class="cx"> // The interference graph.
</span><span class="cx"> HashSet<InterferenceEdge, InterferenceEdgeHash, InterferenceEdgeHashTraits> m_interferenceEdges;
</span><span class="cx"> Vector<Vector<Tmp, 0, UnsafeVectorOverflow, 4>, 0, UnsafeVectorOverflow> m_adjacencyList;
</span></span></pre></div>
<a id="trunkSourceJavaScriptCoreb3testb3cpp"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/b3/testb3.cpp (192354 => 192355)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/b3/testb3.cpp 2015-11-12 07:28:57 UTC (rev 192354)
+++ trunk/Source/JavaScriptCore/b3/testb3.cpp 2015-11-12 07:38:00 UTC (rev 192355)
</span><span class="lines">@@ -2077,6 +2077,29 @@
</span><span class="cx"> compileAndRun<int>(proc, 1, 2);
</span><span class="cx"> }
</span><span class="cx">
</span><ins>+void testSpillFP()
+{
+ Procedure proc;
+ BasicBlock* root = proc.addBlock();
+
+ Vector<Value*> sources;
+ sources.append(root->appendNew<ArgumentRegValue>(proc, Origin(), FPRInfo::argumentFPR0));
+ sources.append(root->appendNew<ArgumentRegValue>(proc, Origin(), FPRInfo::argumentFPR1));
+
+ for (unsigned i = 0; i < 30; ++i) {
+ sources.append(
+ root->appendNew<Value>(proc, Add, Origin(), sources[sources.size() - 1], sources[sources.size() - 2])
+ );
+ }
+
+ Value* total = root->appendNew<ConstDoubleValue>(proc, Origin(), 0.);
+ for (Value* value : sources)
+ total = root->appendNew<Value>(proc, Add, Origin(), total, value);
+
+ root->appendNew<ControlValue>(proc, Return, Origin(), total);
+ compileAndRun<double>(proc, 1.1, 2.5);
+}
+
</ins><span class="cx"> void testBranch()
</span><span class="cx"> {
</span><span class="cx"> Procedure proc;
</span><span class="lines">@@ -3882,6 +3905,7 @@
</span><span class="cx"> RUN(testLoad<uint16_t>(Load16Z, -1000000000));
</span><span class="cx">
</span><span class="cx"> RUN(testSpillGP());
</span><ins>+ RUN(testSpillFP());
</ins><span class="cx">
</span><span class="cx"> RUN(testCallSimple(1, 2));
</span><span class="cx"> RUN(testCallFunctionWithHellaArguments());
</span></span></pre>
</div>
</div>
</body>
</html>