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<dt>Revision</dt> <dd><a href="http://trac.webkit.org/projects/webkit/changeset/192131">192131</a></dd>
<dt>Author</dt> <dd>msaboff@apple.com</dd>
<dt>Date</dt> <dd>2015-11-07 10:11:39 -0800 (Sat, 07 Nov 2015)</dd>
</dl>
<h3>Log Message</h3>
<pre>Add conditional moves to the MacroAssembler
https://bugs.webkit.org/show_bug.cgi?id=150761
Reviewed by Filip Pizlo.
Added moveConditionally, moveConditionallyTest & moveConditionallyDouble to X86 macro assemblers.
Bench tested correct opcodes and operations on X86-64 and X86 for a select number of comparisons.
* assembler/MacroAssemblerX86Common.h:
(JSC::MacroAssemblerX86Common::moveConditionally):
(JSC::MacroAssemblerX86Common::moveConditionallyTest):
(JSC::MacroAssemblerX86Common::moveConditionallyDouble):
* assembler/X86Assembler.h:
(JSC::X86Assembler::cmovcc):
(JSC::X86Assembler::cmovl_rr):
(JSC::X86Assembler::cmovl_mr):
(JSC::X86Assembler::cmovel_rr):
(JSC::X86Assembler::cmovnel_rr):
(JSC::X86Assembler::cmovpl_rr):
(JSC::X86Assembler::cmovnpl_rr):
(JSC::X86Assembler::cmovq_rr):
(JSC::X86Assembler::cmovq_mr):
(JSC::X86Assembler::cmoveq_rr):
(JSC::X86Assembler::cmovneq_rr):
(JSC::X86Assembler::cmovpq_rr):
(JSC::X86Assembler::cmovnpq_rr):
(JSC::X86Assembler::X86InstructionFormatter::twoByteOp64):</pre>
<h3>Modified Paths</h3>
<ul>
<li><a href="#trunkSourceJavaScriptCoreChangeLog">trunk/Source/JavaScriptCore/ChangeLog</a></li>
<li><a href="#trunkSourceJavaScriptCoreassemblerMacroAssemblerX86Commonh">trunk/Source/JavaScriptCore/assembler/MacroAssemblerX86Common.h</a></li>
<li><a href="#trunkSourceJavaScriptCoreassemblerX86Assemblerh">trunk/Source/JavaScriptCore/assembler/X86Assembler.h</a></li>
</ul>
</div>
<div id="patch">
<h3>Diff</h3>
<a id="trunkSourceJavaScriptCoreChangeLog"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/ChangeLog (192130 => 192131)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/ChangeLog 2015-11-07 17:17:47 UTC (rev 192130)
+++ trunk/Source/JavaScriptCore/ChangeLog 2015-11-07 18:11:39 UTC (rev 192131)
</span><span class="lines">@@ -1,3 +1,33 @@
</span><ins>+2015-11-07 Michael Saboff <msaboff@apple.com>
+
+ Add conditional moves to the MacroAssembler
+ https://bugs.webkit.org/show_bug.cgi?id=150761
+
+ Reviewed by Filip Pizlo.
+
+ Added moveConditionally, moveConditionallyTest & moveConditionallyDouble to X86 macro assemblers.
+ Bench tested correct opcodes and operations on X86-64 and X86 for a select number of comparisons.
+
+ * assembler/MacroAssemblerX86Common.h:
+ (JSC::MacroAssemblerX86Common::moveConditionally):
+ (JSC::MacroAssemblerX86Common::moveConditionallyTest):
+ (JSC::MacroAssemblerX86Common::moveConditionallyDouble):
+ * assembler/X86Assembler.h:
+ (JSC::X86Assembler::cmovcc):
+ (JSC::X86Assembler::cmovl_rr):
+ (JSC::X86Assembler::cmovl_mr):
+ (JSC::X86Assembler::cmovel_rr):
+ (JSC::X86Assembler::cmovnel_rr):
+ (JSC::X86Assembler::cmovpl_rr):
+ (JSC::X86Assembler::cmovnpl_rr):
+ (JSC::X86Assembler::cmovq_rr):
+ (JSC::X86Assembler::cmovq_mr):
+ (JSC::X86Assembler::cmoveq_rr):
+ (JSC::X86Assembler::cmovneq_rr):
+ (JSC::X86Assembler::cmovpq_rr):
+ (JSC::X86Assembler::cmovnpq_rr):
+ (JSC::X86Assembler::X86InstructionFormatter::twoByteOp64):
+
</ins><span class="cx"> 2015-11-06 Saam barati <sbarati@apple.com>
</span><span class="cx">
</span><span class="cx"> Control Flow Profiler should keep execution counts of basic blocks
</span></span></pre></div>
<a id="trunkSourceJavaScriptCoreassemblerMacroAssemblerX86Commonh"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/assembler/MacroAssemblerX86Common.h (192130 => 192131)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/assembler/MacroAssemblerX86Common.h 2015-11-07 17:17:47 UTC (rev 192130)
+++ trunk/Source/JavaScriptCore/assembler/MacroAssemblerX86Common.h 2015-11-07 18:11:39 UTC (rev 192131)
</span><span class="lines">@@ -1046,6 +1046,54 @@
</span><span class="cx"> m_assembler.movq_i64r(imm.m_value, dest);
</span><span class="cx"> }
</span><span class="cx">
</span><ins>+ void moveConditionally(RelationalCondition cond, RegisterID left, RegisterID right, RegisterID src, RegisterID dest)
+ {
+ m_assembler.cmpq_rr(right, left);
+ m_assembler.cmovq_rr(x86Condition(cond), src, dest);
+ }
+
+ void moveConditionallyTest(ResultCondition cond, RegisterID testReg, RegisterID mask, RegisterID src, RegisterID dest)
+ {
+ m_assembler.testq_rr(testReg, mask);
+ m_assembler.cmovq_rr(x86Condition(cond), src, dest);
+ }
+
+ void moveConditionallyDouble(DoubleCondition cond, FPRegisterID left, FPRegisterID right, RegisterID src, RegisterID dest)
+ {
+ ASSERT(isSSE2Present());
+
+ if (cond & DoubleConditionBitInvert)
+ m_assembler.ucomisd_rr(left, right);
+ else
+ m_assembler.ucomisd_rr(right, left);
+
+ if (cond == DoubleEqual) {
+ if (left == right) {
+ m_assembler.cmovnpq_rr(src, dest);
+ return;
+ }
+
+ Jump isUnordered(m_assembler.jp());
+ m_assembler.cmoveq_rr(src, dest);
+ isUnordered.link(this);
+ return;
+ }
+
+ if (cond == DoubleNotEqualOrUnordered) {
+ if (left == right) {
+ m_assembler.cmovpq_rr(src, dest);
+ return;
+ }
+
+ m_assembler.cmovpq_rr(src, dest);
+ m_assembler.cmovneq_rr(src, dest);
+ return;
+ }
+
+ ASSERT(!(cond & DoubleConditionBitSpecial));
+ m_assembler.cmovq_rr(static_cast<X86Assembler::Condition>(cond & ~DoubleConditionBits), src, dest);
+ }
+
</ins><span class="cx"> void swap(RegisterID reg1, RegisterID reg2)
</span><span class="cx"> {
</span><span class="cx"> if (reg1 != reg2)
</span><span class="lines">@@ -1078,6 +1126,54 @@
</span><span class="cx"> m_assembler.movl_i32r(imm.asIntptr(), dest);
</span><span class="cx"> }
</span><span class="cx">
</span><ins>+ void moveConditionally(RelationalCondition cond, RegisterID left, RegisterID right, RegisterID src, RegisterID dest)
+ {
+ m_assembler.cmpl_rr(right, left);
+ m_assembler.cmovl_rr(x86Condition(cond), src, dest);
+ }
+
+ void moveConditionallyTest(ResultCondition cond, RegisterID testReg, RegisterID mask, RegisterID src, RegisterID dest)
+ {
+ m_assembler.testl_rr(testReg, mask);
+ m_assembler.cmovl_rr(x86Condition(cond), src, dest);
+ }
+
+ void moveConditionallyDouble(DoubleCondition cond, FPRegisterID left, FPRegisterID right, RegisterID src, RegisterID dest)
+ {
+ ASSERT(isSSE2Present());
+
+ if (cond & DoubleConditionBitInvert)
+ m_assembler.ucomisd_rr(left, right);
+ else
+ m_assembler.ucomisd_rr(right, left);
+
+ if (cond == DoubleEqual) {
+ if (left == right) {
+ m_assembler.cmovnpl_rr(src, dest);
+ return;
+ }
+
+ Jump isUnordered(m_assembler.jp());
+ m_assembler.cmovel_rr(src, dest);
+ isUnordered.link(this);
+ return;
+ }
+
+ if (cond == DoubleNotEqualOrUnordered) {
+ if (left == right) {
+ m_assembler.cmovpl_rr(src, dest);
+ return;
+ }
+
+ m_assembler.cmovpl_rr(src, dest);
+ m_assembler.cmovnel_rr(src, dest);
+ return;
+ }
+
+ ASSERT(!(cond & DoubleConditionBitSpecial));
+ m_assembler.cmovl_rr(static_cast<X86Assembler::Condition>(cond & ~DoubleConditionBits), src, dest);
+ }
+
</ins><span class="cx"> void swap(RegisterID reg1, RegisterID reg2)
</span><span class="cx"> {
</span><span class="cx"> if (reg1 != reg2)
</span></span></pre></div>
<a id="trunkSourceJavaScriptCoreassemblerX86Assemblerh"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/assembler/X86Assembler.h (192130 => 192131)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/assembler/X86Assembler.h 2015-11-07 17:17:47 UTC (rev 192130)
+++ trunk/Source/JavaScriptCore/assembler/X86Assembler.h 2015-11-07 18:11:39 UTC (rev 192131)
</span><span class="lines">@@ -248,6 +248,7 @@
</span><span class="cx"> OP2_CVTSI2SD_VsdEd = 0x2A,
</span><span class="cx"> OP2_CVTTSD2SI_GdWsd = 0x2C,
</span><span class="cx"> OP2_UCOMISD_VsdWsd = 0x2E,
</span><ins>+ OP2_CMOVCC = 0x40,
</ins><span class="cx"> OP2_ADDSD_VsdWsd = 0x58,
</span><span class="cx"> OP2_MULSD_VsdWsd = 0x59,
</span><span class="cx"> OP2_CVTSD2SS_VsdWsd = 0x5A,
</span><span class="lines">@@ -279,6 +280,12 @@
</span><span class="cx"> OP3_MFENCE = 0xF0,
</span><span class="cx"> } ThreeByteOpcodeID;
</span><span class="cx">
</span><ins>+
+ TwoByteOpcodeID cmovcc(Condition cond)
+ {
+ return (TwoByteOpcodeID)(OP2_CMOVCC + cond);
+ }
+
</ins><span class="cx"> TwoByteOpcodeID jccRel32(Condition cond)
</span><span class="cx"> {
</span><span class="cx"> return (TwoByteOpcodeID)(OP2_JCC_rel32 + cond);
</span><span class="lines">@@ -1589,6 +1596,83 @@
</span><span class="cx"> m_formatter.twoByteOp8(OP2_MOVZX_GvEb, dst, src);
</span><span class="cx"> }
</span><span class="cx">
</span><ins>+ void cmovl_rr(Condition cond, RegisterID src, RegisterID dst)
+ {
+ m_formatter.twoByteOp(cmovcc(cond), src, dst);
+ }
+
+ void cmovl_mr(Condition cond, int offset, RegisterID base, RegisterID dst)
+ {
+ m_formatter.twoByteOp(cmovcc(cond), dst, base, offset);
+ }
+
+ void cmovl_mr(Condition cond, int offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
+ {
+ m_formatter.twoByteOp(cmovcc(cond), dst, base, index, scale, offset);
+ }
+
+ void cmovel_rr(RegisterID src, RegisterID dst)
+ {
+ m_formatter.twoByteOp(cmovcc(ConditionE), src, dst);
+ }
+
+ void cmovnel_rr(RegisterID src, RegisterID dst)
+ {
+ m_formatter.twoByteOp(cmovcc(ConditionNE), src, dst);
+ }
+
+ void cmovpl_rr(RegisterID src, RegisterID dst)
+ {
+ m_formatter.twoByteOp(cmovcc(ConditionP), src, dst);
+ }
+
+ void cmovnpl_rr(RegisterID src, RegisterID dst)
+ {
+ m_formatter.twoByteOp(cmovcc(ConditionNP), src, dst);
+ }
+
+#if CPU(X86_64)
+ void cmovq_rr(Condition cond, RegisterID src, RegisterID dst)
+ {
+ m_formatter.twoByteOp64(cmovcc(cond), src, dst);
+ }
+
+ void cmovq_mr(Condition cond, int offset, RegisterID base, RegisterID dst)
+ {
+ m_formatter.twoByteOp64(cmovcc(cond), dst, base, offset);
+ }
+
+ void cmovq_mr(Condition cond, int offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
+ {
+ m_formatter.twoByteOp64(cmovcc(cond), dst, base, index, scale, offset);
+ }
+
+ void cmoveq_rr(RegisterID src, RegisterID dst)
+ {
+ m_formatter.twoByteOp64(cmovcc(ConditionE), src, dst);
+ }
+
+ void cmovneq_rr(RegisterID src, RegisterID dst)
+ {
+ m_formatter.twoByteOp64(cmovcc(ConditionNE), src, dst);
+ }
+
+ void cmovpq_rr(RegisterID src, RegisterID dst)
+ {
+ m_formatter.twoByteOp64(cmovcc(ConditionP), src, dst);
+ }
+
+ void cmovnpq_rr(RegisterID src, RegisterID dst)
+ {
+ m_formatter.twoByteOp64(cmovcc(ConditionNP), src, dst);
+ }
+#else
+ void cmovl_mr(Condition cond, const void* addr, RegisterID dst)
+ {
+ m_formatter.twoByteOp(cmovcc(cond), dst, addr);
+ }
+#endif
+
</ins><span class="cx"> void leal_mr(int offset, RegisterID base, RegisterID dst)
</span><span class="cx"> {
</span><span class="cx"> m_formatter.oneByteOp(OP_LEA, dst, base, offset);
</span><span class="lines">@@ -2577,6 +2661,24 @@
</span><span class="cx"> m_buffer.putByteUnchecked(opcode);
</span><span class="cx"> registerModRM(reg, rm);
</span><span class="cx"> }
</span><ins>+
+ void twoByteOp64(TwoByteOpcodeID opcode, int reg, RegisterID base, int offset)
+ {
+ m_buffer.ensureSpace(maxInstructionSize);
+ emitRexW(reg, 0, base);
+ m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE);
+ m_buffer.putByteUnchecked(opcode);
+ memoryModRM(reg, base, offset);
+ }
+
+ void twoByteOp64(TwoByteOpcodeID opcode, int reg, RegisterID base, RegisterID index, int scale, int offset)
+ {
+ m_buffer.ensureSpace(maxInstructionSize);
+ emitRexW(reg, index, base);
+ m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE);
+ m_buffer.putByteUnchecked(opcode);
+ memoryModRM(reg, base, index, scale, offset);
+ }
</ins><span class="cx"> #endif
</span><span class="cx">
</span><span class="cx"> // Byte-operands:
</span></span></pre>
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