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<title>[187877] branches/jsc-tailcall/Source/JavaScriptCore</title>
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<dt>Revision</dt> <dd><a href="http://trac.webkit.org/projects/webkit/changeset/187877">187877</a></dd>
<dt>Author</dt> <dd>msaboff@apple.com</dd>
<dt>Date</dt> <dd>2015-08-04 12:47:44 -0700 (Tue, 04 Aug 2015)</dd>
</dl>
<h3>Log Message</h3>
<pre>jsc-tailcall: Align callee save registers names across LLInt and JITs
https://bugs.webkit.org/show_bug.cgi?id=147640
Reviewed by Basile Clement.
Added callee save register aliases to both the LLInt and JITs and set the aliases to
the same register. As a result, regCS0 in the JIT is the same as csr0 in the LLInt.
Some registers are unused in either the LLInt or JITs.
This is in preparation for properly handling callee save register restoration during exception
processing as all tiers are involved in the restoration process of all callee saves.
* jit/GPRInfo.h:
(JSC::GPRInfo::toIndex):
* jit/RegisterSet.cpp:
(JSC::RegisterSet::allVMCalleeSaveRegisters):
(JSC::RegisterSet::baselineCalleeSaveRegisters):
(JSC::RegisterSet::dfgCalleeSaveRegisters):
* llint/LowLevelInterpreter.asm:
* offlineasm/registers.rb:
* offlineasm/x86.rb:</pre>
<h3>Modified Paths</h3>
<ul>
<li><a href="#branchesjsctailcallSourceJavaScriptCoreChangeLog">branches/jsc-tailcall/Source/JavaScriptCore/ChangeLog</a></li>
<li><a href="#branchesjsctailcallSourceJavaScriptCorejitGPRInfoh">branches/jsc-tailcall/Source/JavaScriptCore/jit/GPRInfo.h</a></li>
<li><a href="#branchesjsctailcallSourceJavaScriptCorejitRegisterSetcpp">branches/jsc-tailcall/Source/JavaScriptCore/jit/RegisterSet.cpp</a></li>
<li><a href="#branchesjsctailcallSourceJavaScriptCorellintLowLevelInterpreterasm">branches/jsc-tailcall/Source/JavaScriptCore/llint/LowLevelInterpreter.asm</a></li>
<li><a href="#branchesjsctailcallSourceJavaScriptCoreofflineasmregistersrb">branches/jsc-tailcall/Source/JavaScriptCore/offlineasm/registers.rb</a></li>
<li><a href="#branchesjsctailcallSourceJavaScriptCoreofflineasmx86rb">branches/jsc-tailcall/Source/JavaScriptCore/offlineasm/x86.rb</a></li>
</ul>
</div>
<div id="patch">
<h3>Diff</h3>
<a id="branchesjsctailcallSourceJavaScriptCoreChangeLog"></a>
<div class="modfile"><h4>Modified: branches/jsc-tailcall/Source/JavaScriptCore/ChangeLog (187876 => 187877)</h4>
<pre class="diff"><span>
<span class="info">--- branches/jsc-tailcall/Source/JavaScriptCore/ChangeLog 2015-08-04 19:22:52 UTC (rev 187876)
+++ branches/jsc-tailcall/Source/JavaScriptCore/ChangeLog 2015-08-04 19:47:44 UTC (rev 187877)
</span><span class="lines">@@ -1,3 +1,27 @@
</span><ins>+2015-08-04 Michael Saboff <msaboff@apple.com>
+
+ jsc-tailcall: Align callee save registers names across LLInt and JITs
+ https://bugs.webkit.org/show_bug.cgi?id=147640
+
+ Reviewed by Basile Clement.
+
+ Added callee save register aliases to both the LLInt and JITs and set the aliases to
+ the same register. As a result, regCS0 in the JIT is the same as csr0 in the LLInt.
+ Some registers are unused in either the LLInt or JITs.
+
+ This is in preparation for properly handling callee save register restoration during exception
+ processing as all tiers are involved in the restoration process of all callee saves.
+
+ * jit/GPRInfo.h:
+ (JSC::GPRInfo::toIndex):
+ * jit/RegisterSet.cpp:
+ (JSC::RegisterSet::allVMCalleeSaveRegisters):
+ (JSC::RegisterSet::baselineCalleeSaveRegisters):
+ (JSC::RegisterSet::dfgCalleeSaveRegisters):
+ * llint/LowLevelInterpreter.asm:
+ * offlineasm/registers.rb:
+ * offlineasm/x86.rb:
+
</ins><span class="cx"> 2015-08-04 Basile Clement <basile_clement@apple.com>
</span><span class="cx">
</span><span class="cx"> jsc-tailcall: We should abortWithReason() if we ever return from a tail call
</span></span></pre></div>
<a id="branchesjsctailcallSourceJavaScriptCorejitGPRInfoh"></a>
<div class="modfile"><h4>Modified: branches/jsc-tailcall/Source/JavaScriptCore/jit/GPRInfo.h (187876 => 187877)</h4>
<pre class="diff"><span>
<span class="info">--- branches/jsc-tailcall/Source/JavaScriptCore/jit/GPRInfo.h 2015-08-04 19:22:52 UTC (rev 187876)
+++ branches/jsc-tailcall/Source/JavaScriptCore/jit/GPRInfo.h 2015-08-04 19:47:44 UTC (rev 187877)
</span><span class="lines">@@ -403,15 +403,17 @@
</span><span class="cx"> #endif
</span><span class="cx">
</span><span class="cx"> static const GPRReg regCS0 = X86Registers::ebx;
</span><ins>+
+#if !OS(WINDOWS)
</ins><span class="cx"> static const GPRReg regCS1 = X86Registers::r12;
</span><span class="cx"> static const GPRReg regCS2 = X86Registers::r13;
</span><del>-
-#if !OS(WINDOWS)
</del><span class="cx"> static const GPRReg regCS3 = X86Registers::r14;
</span><span class="cx"> static const GPRReg regCS4 = X86Registers::r15;
</span><span class="cx"> #else
</span><del>- static const GPRReg regCS3 = X86Registers::esi;
- static const GPRReg regCS4 = X86Registers::edi;
</del><ins>+ static const GPRReg regCS1 = X86Registers::esi;
+ static const GPRReg regCS2 = X86Registers::edi;
+ static const GPRReg regCS3 = X86Registers::r12;
+ static const GPRReg regCS4 = X86Registers::r13;
</ins><span class="cx"> static const GPRReg regCS5 = X86Registers::r14;
</span><span class="cx"> static const GPRReg regCS6 = X86Registers::r15;
</span><span class="cx"> #endif
</span><span class="lines">@@ -474,7 +476,7 @@
</span><span class="cx"> #if !OS(WINDOWS)
</span><span class="cx"> static const unsigned indexForRegister[16] = { 0, 3, 2, 8, InvalidIndex, InvalidIndex, 1, 6, 4, 7, 5, InvalidIndex, 9, 10, InvalidIndex, InvalidIndex };
</span><span class="cx"> #else
</span><del>- static const unsigned indexForRegister[16] = { 0, 5, 1, 6, InvalidIndex, InvalidIndex, 9, 10, 2, 3, 4, InvalidIndex, 7, 8, InvalidIndex, InvalidIndex };
</del><ins>+ static const unsigned indexForRegister[16] = { 0, 5, 1, 6, InvalidIndex, InvalidIndex, 7, 8, 2, 3, 4, InvalidIndex, 9, 10, InvalidIndex, InvalidIndex };
</ins><span class="cx"> #endif
</span><span class="cx"> return indexForRegister[reg];
</span><span class="cx"> }
</span><span class="lines">@@ -612,8 +614,9 @@
</span><span class="cx"> static const GPRReg regT13 = ARM64Registers::x13;
</span><span class="cx"> static const GPRReg regT14 = ARM64Registers::x14;
</span><span class="cx"> static const GPRReg regT15 = ARM64Registers::x15;
</span><del>- static const GPRReg regCS0 = ARM64Registers::x27; // tagTypeNumber
- static const GPRReg regCS1 = ARM64Registers::x28; // tagMask
</del><ins>+ static const GPRReg regCS0 = ARM64Registers::x26; // Used by LLInt only
+ static const GPRReg regCS1 = ARM64Registers::x27; // tagTypeNumber
+ static const GPRReg regCS2 = ARM64Registers::x28; // tagMask
</ins><span class="cx"> // These constants provide the names for the general purpose argument & return value registers.
</span><span class="cx"> static const GPRReg argumentGPR0 = ARM64Registers::x0; // regT0
</span><span class="cx"> static const GPRReg argumentGPR1 = ARM64Registers::x1; // regT1
</span></span></pre></div>
<a id="branchesjsctailcallSourceJavaScriptCorejitRegisterSetcpp"></a>
<div class="modfile"><h4>Modified: branches/jsc-tailcall/Source/JavaScriptCore/jit/RegisterSet.cpp (187876 => 187877)</h4>
<pre class="diff"><span>
<span class="info">--- branches/jsc-tailcall/Source/JavaScriptCore/jit/RegisterSet.cpp 2015-08-04 19:22:52 UTC (rev 187876)
+++ branches/jsc-tailcall/Source/JavaScriptCore/jit/RegisterSet.cpp 2015-08-04 19:47:44 UTC (rev 187877)
</span><span class="lines">@@ -146,11 +146,11 @@
</span><span class="cx"> #elif CPU(ARM_THUMB2)
</span><span class="cx"> #elif CPU(ARM_TRADITIONAL)
</span><span class="cx"> #elif CPU(ARM64)
</span><del>- result.set(ARM64Registers::x26);
- ASSERT(GPRInfo::regCS0 == GPRInfo::tagTypeNumberRegister);
- ASSERT(GPRInfo::regCS1 == GPRInfo::tagMaskRegister);
</del><span class="cx"> result.set(GPRInfo::regCS0);
</span><ins>+ ASSERT(GPRInfo::regCS1 == GPRInfo::tagTypeNumberRegister);
+ ASSERT(GPRInfo::regCS2 == GPRInfo::tagMaskRegister);
</ins><span class="cx"> result.set(GPRInfo::regCS1);
</span><ins>+ result.set(GPRInfo::regCS2);
</ins><span class="cx"> #elif CPU(MIPS)
</span><span class="cx"> #elif CPU(SH4)
</span><span class="cx"> #else
</span><span class="lines">@@ -180,10 +180,10 @@
</span><span class="cx"> #elif CPU(ARM_THUMB2)
</span><span class="cx"> #elif CPU(ARM_TRADITIONAL)
</span><span class="cx"> #elif CPU(ARM64)
</span><del>- ASSERT(GPRInfo::regCS0 == GPRInfo::tagTypeNumberRegister);
- ASSERT(GPRInfo::regCS1 == GPRInfo::tagMaskRegister);
- result.set(GPRInfo::regCS0);
</del><ins>+ ASSERT(GPRInfo::regCS1 == GPRInfo::tagTypeNumberRegister);
+ ASSERT(GPRInfo::regCS2 == GPRInfo::tagMaskRegister);
</ins><span class="cx"> result.set(GPRInfo::regCS1);
</span><ins>+ result.set(GPRInfo::regCS2);
</ins><span class="cx"> #elif CPU(MIPS)
</span><span class="cx"> #elif CPU(SH4)
</span><span class="cx"> #else
</span><span class="lines">@@ -216,10 +216,10 @@
</span><span class="cx"> #elif CPU(ARM_THUMB2)
</span><span class="cx"> #elif CPU(ARM_TRADITIONAL)
</span><span class="cx"> #elif CPU(ARM64)
</span><del>- ASSERT(GPRInfo::regCS0 == GPRInfo::tagTypeNumberRegister);
- ASSERT(GPRInfo::regCS1 == GPRInfo::tagMaskRegister);
- result.set(GPRInfo::regCS0);
</del><ins>+ ASSERT(GPRInfo::regCS1 == GPRInfo::tagTypeNumberRegister);
+ ASSERT(GPRInfo::regCS2 == GPRInfo::tagMaskRegister);
</ins><span class="cx"> result.set(GPRInfo::regCS1);
</span><ins>+ result.set(GPRInfo::regCS2);
</ins><span class="cx"> #elif CPU(MIPS)
</span><span class="cx"> #elif CPU(SH4)
</span><span class="cx"> #else
</span></span></pre></div>
<a id="branchesjsctailcallSourceJavaScriptCorellintLowLevelInterpreterasm"></a>
<div class="modfile"><h4>Modified: branches/jsc-tailcall/Source/JavaScriptCore/llint/LowLevelInterpreter.asm (187876 => 187877)</h4>
<pre class="diff"><span>
<span class="info">--- branches/jsc-tailcall/Source/JavaScriptCore/llint/LowLevelInterpreter.asm 2015-08-04 19:22:52 UTC (rev 187876)
+++ branches/jsc-tailcall/Source/JavaScriptCore/llint/LowLevelInterpreter.asm 2015-08-04 19:47:44 UTC (rev 187877)
</span><span class="lines">@@ -107,9 +107,10 @@
</span><span class="cx"> # - t4 and t5 are never argument registers, t3 can only be a3, t1 can only be
</span><span class="cx"> # a1; but t0 and t2 can be either a0 or a2.
</span><span class="cx"> #
</span><del>-# - On 64 bits, csr0, csr1 and csr2 are available as callee-save registers.
-# csr0 is used to store the PC base, while csr1 and csr2 are used to store
-# special tag values. Don't use them for anything else.
</del><ins>+# - On 64 bits, csr0, csr1, csr2 and optionally csr3, csr4, csr5 and csr6
+# are available as callee-save registers.
+# csr0 is used to store the PC base, while the last two csr registers are used
+# to store special tag values. Don't use them for anything else.
</ins><span class="cx"> #
</span><span class="cx"> # Additional platform-specific details (you shouldn't rely on this remaining
</span><span class="cx"> # true):
</span><span class="lines">@@ -239,9 +240,17 @@
</span><span class="cx"> # This requires an add before the call, and a sub after.
</span><span class="cx"> const PC = t4
</span><span class="cx"> const PB = csr0
</span><del>- const tagTypeNumber = csr1
- const tagMask = csr2
-
</del><ins>+ if ARM64
+ const tagTypeNumber = csr1
+ const tagMask = csr2
+ elsif X86_64
+ const tagTypeNumber = csr3
+ const tagMask = csr4
+ elsif X86_64_WIN
+ const tagTypeNumber = csr5
+ const tagMask = csr6
+ end
+
</ins><span class="cx"> macro loadisFromInstruction(offset, dest)
</span><span class="cx"> loadis offset * 8[PB, PC, 8], dest
</span><span class="cx"> end
</span><span class="lines">@@ -546,13 +555,13 @@
</span><span class="cx"> elsif X86
</span><span class="cx"> elsif X86_WIN
</span><span class="cx"> elsif X86_64
</span><del>- storep csr2, -8[cfr]
- storep csr1, -16[cfr]
</del><ins>+ storep csr4, -8[cfr]
+ storep csr3, -16[cfr]
</ins><span class="cx"> storep csr0, -24[cfr]
</span><span class="cx"> elsif X86_64_WIN
</span><span class="cx"> storep t4, -8[cfr]
</span><del>- storep csr2, -16[cfr]
- storep csr1, -24[cfr]
</del><ins>+ storep csr6, -16[cfr]
+ storep csr5, -24[cfr]
</ins><span class="cx"> storep csr0, -32[cfr]
</span><span class="cx"> end
</span><span class="cx"> end
</span><span class="lines">@@ -570,12 +579,12 @@
</span><span class="cx"> elsif X86_WIN
</span><span class="cx"> elsif X86_64
</span><span class="cx"> loadp -24[cfr], csr0
</span><del>- loadp -16[cfr], csr1
- loadp -8[cfr], csr2
</del><ins>+ loadp -16[cfr], csr3
+ loadp -8[cfr], csr4
</ins><span class="cx"> elsif X86_64_WIN
</span><span class="cx"> loadp -32[cfr], csr0
</span><del>- loadp -24[cfr], csr1
- loadp -16[cfr], csr2
</del><ins>+ loadp -24[cfr], csr5
+ loadp -16[cfr], csr6
</ins><span class="cx"> loadp -8[cfr], t4
</span><span class="cx"> end
</span><span class="cx"> end
</span></span></pre></div>
<a id="branchesjsctailcallSourceJavaScriptCoreofflineasmregistersrb"></a>
<div class="modfile"><h4>Modified: branches/jsc-tailcall/Source/JavaScriptCore/offlineasm/registers.rb (187876 => 187877)</h4>
<pre class="diff"><span>
<span class="info">--- branches/jsc-tailcall/Source/JavaScriptCore/offlineasm/registers.rb 2015-08-04 19:22:52 UTC (rev 187876)
+++ branches/jsc-tailcall/Source/JavaScriptCore/offlineasm/registers.rb 2015-08-04 19:47:44 UTC (rev 187877)
</span><span class="lines">@@ -43,8 +43,12 @@
</span><span class="cx"> "pc",
</span><span class="cx"> # 64-bit only registers:
</span><span class="cx"> "csr0",
</span><del>- "csr1", # tag type number register
- "csr2" # tag mask register
</del><ins>+ "csr1",
+ "csr2",
+ "csr3",
+ "csr4",
+ "csr5",
+ "csr6"
</ins><span class="cx"> ]
</span><span class="cx">
</span><span class="cx"> FPRS =
</span></span></pre></div>
<a id="branchesjsctailcallSourceJavaScriptCoreofflineasmx86rb"></a>
<div class="modfile"><h4>Modified: branches/jsc-tailcall/Source/JavaScriptCore/offlineasm/x86.rb (187876 => 187877)</h4>
<pre class="diff"><span>
<span class="info">--- branches/jsc-tailcall/Source/JavaScriptCore/offlineasm/x86.rb 2015-08-04 19:22:52 UTC (rev 187876)
+++ branches/jsc-tailcall/Source/JavaScriptCore/offlineasm/x86.rb 2015-08-04 19:47:44 UTC (rev 187877)
</span><span class="lines">@@ -51,10 +51,10 @@
</span><span class="cx"> # r8 => t4
</span><span class="cx"> # r10 => t5
</span><span class="cx"> # rbx => csr0 (callee-save, PB, unused in baseline)
</span><del>-# r12 => (callee-save)
-# r13 => (callee-save)
-# r14 => csr1 (callee-save, tagTypeNumber)
-# r15 => csr2 (callee-save, tagMask)
</del><ins>+# r12 => csr1 (callee-save)
+# r13 => csr2 (callee-save)
+# r14 => csr3 (callee-save, tagTypeNumber)
+# r15 => csr4 (callee-save, tagMask)
</ins><span class="cx"> # rsp => sp
</span><span class="cx"> # rbp => cfr
</span><span class="cx"> # r11 => (scratch)
</span><span class="lines">@@ -69,13 +69,13 @@
</span><span class="cx"> # r8 => t2, a2
</span><span class="cx"> # r9 => t3, a3
</span><span class="cx"> # r10 => t4
</span><del>-# rsi => (callee-save)
</del><span class="cx"> # rbx => csr0 (callee-save, PB, unused in baseline)
</span><del>-# rdi => (callee-save)
-# r12 => (callee-save)
-# r13 => (callee-save)
-# r14 => csr1 (callee-save, tagTypeNumber)
-# r15 => csr2 (callee-save, tagMask)
</del><ins>+# rsi => csr1 (callee-save)
+# rdi => csr2 (callee-save)
+# r12 => csr3 (callee-save)
+# r13 => csr4 (callee-save)
+# r14 => csr5 (callee-save, tagTypeNumber)
+# r15 => csr6 (callee-save, tagMask)
</ins><span class="cx"> # rsp => sp
</span><span class="cx"> # rbp => cfr
</span><span class="cx"> # r11 => (scratch)
</span><span class="lines">@@ -290,9 +290,20 @@
</span><span class="cx"> when "csr0"
</span><span class="cx"> "ebx"
</span><span class="cx"> when "csr1"
</span><del>- "r14"
</del><ins>+ "r12"
</ins><span class="cx"> when "csr2"
</span><ins>+ "r13"
+ when "csr3"
+ isWin ? "esi" : "r14"
+ when "csr4"
+ isWin ? "edi" : "r15"
</ins><span class="cx"> "r15"
</span><ins>+ when "csr5"
+ raise "cannot use register #{name} on X86-64" unless isWin
+ "r14"
+ when "csr6"
+ raise "cannot use register #{name} on X86-64" unless isWin
+ "r15"
</ins><span class="cx"> when "cfr"
</span><span class="cx"> "ebp"
</span><span class="cx"> when "sp"
</span></span></pre>
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