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<dt>Revision</dt> <dd><a href="http://trac.webkit.org/projects/webkit/changeset/187670">187670</a></dd>
<dt>Author</dt> <dd>msaboff@apple.com</dd>
<dt>Date</dt> <dd>2015-07-31 13:01:59 -0700 (Fri, 31 Jul 2015)</dd>
</dl>
<h3>Log Message</h3>
<pre>jsc-tailcall:Eliminate the unsafe use of regT5 in arityFixupGenerator() for X86-64 Windows
https://bugs.webkit.org/show_bug.cgi?id=147499
Reviewed by Basile Clement.
For X86-64, Windows, regT0 is free so use that register instead of regT5.
* jit/ThunkGenerators.cpp:
(JSC::arityFixupGenerator):</pre>
<h3>Modified Paths</h3>
<ul>
<li><a href="#branchesjsctailcallSourceJavaScriptCoreChangeLog">branches/jsc-tailcall/Source/JavaScriptCore/ChangeLog</a></li>
<li><a href="#branchesjsctailcallSourceJavaScriptCorejitThunkGeneratorscpp">branches/jsc-tailcall/Source/JavaScriptCore/jit/ThunkGenerators.cpp</a></li>
</ul>
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<h3>Diff</h3>
<a id="branchesjsctailcallSourceJavaScriptCoreChangeLog"></a>
<div class="modfile"><h4>Modified: branches/jsc-tailcall/Source/JavaScriptCore/ChangeLog (187669 => 187670)</h4>
<pre class="diff"><span>
<span class="info">--- branches/jsc-tailcall/Source/JavaScriptCore/ChangeLog 2015-07-31 19:43:43 UTC (rev 187669)
+++ branches/jsc-tailcall/Source/JavaScriptCore/ChangeLog 2015-07-31 20:01:59 UTC (rev 187670)
</span><span class="lines">@@ -1,3 +1,15 @@
</span><ins>+2015-07-31 Michael Saboff <msaboff@apple.com>
+
+ jsc-tailcall:Eliminate the unsafe use of regT5 in arityFixupGenerator() for X86-64 Windows
+ https://bugs.webkit.org/show_bug.cgi?id=147499
+
+ Reviewed by Basile Clement.
+
+ For X86-64, Windows, regT0 is free so use that register instead of regT5.
+
+ * jit/ThunkGenerators.cpp:
+ (JSC::arityFixupGenerator):
+
</ins><span class="cx"> 2015-07-30 Michael Saboff <msaboff@apple.com>
</span><span class="cx">
</span><span class="cx"> jsc-tailcall: LLint, Baseline and DFG JIT should save & restore platform's callee-save registers
</span></span></pre></div>
<a id="branchesjsctailcallSourceJavaScriptCorejitThunkGeneratorscpp"></a>
<div class="modfile"><h4>Modified: branches/jsc-tailcall/Source/JavaScriptCore/jit/ThunkGenerators.cpp (187669 => 187670)</h4>
<pre class="diff"><span>
<span class="info">--- branches/jsc-tailcall/Source/JavaScriptCore/jit/ThunkGenerators.cpp 2015-07-31 19:43:43 UTC (rev 187669)
+++ branches/jsc-tailcall/Source/JavaScriptCore/jit/ThunkGenerators.cpp 2015-07-31 20:01:59 UTC (rev 187670)
</span><span class="lines">@@ -365,8 +365,13 @@
</span><span class="cx"> JSInterfaceJIT jit(vm);
</span><span class="cx">
</span><span class="cx"> // We enter with fixup count, in aligned stack units, in argumentGPR0 and the return thunk in argumentGPR1
</span><del>- // We have the guarantee that a0, a1, a2, t3, t4 and t5 are all distinct :-)
</del><ins>+ // We have the guarantee that a0, a1, a2, t3, t4 and t5 (or t0 for Windows) are all distinct :-)
</ins><span class="cx"> #if USE(JSVALUE64)
</span><ins>+#if OS(WINDOWS)
+ const GPRReg extraTemp = JSInterfaceJIT::regT0;
+#else
+ const GPRReg extraTemp = JSInterfaceJIT::regT5;
+#endif
</ins><span class="cx"> # if CPU(X86_64)
</span><span class="cx"> jit.pop(JSInterfaceJIT::regT4);
</span><span class="cx"> # endif
</span><span class="lines">@@ -378,25 +383,25 @@
</span><span class="cx">
</span><span class="cx"> // Move current frame down argumentGPR0 number of slots
</span><span class="cx"> JSInterfaceJIT::Label copyLoop(jit.label());
</span><del>- jit.load64(JSInterfaceJIT::regT3, JSInterfaceJIT::regT5);
- jit.store64(JSInterfaceJIT::regT5, MacroAssembler::BaseIndex(JSInterfaceJIT::regT3, JSInterfaceJIT::argumentGPR0, JSInterfaceJIT::TimesEight));
</del><ins>+ jit.load64(JSInterfaceJIT::regT3, extraTemp);
+ jit.store64(extraTemp, MacroAssembler::BaseIndex(JSInterfaceJIT::regT3, JSInterfaceJIT::argumentGPR0, JSInterfaceJIT::TimesEight));
</ins><span class="cx"> jit.addPtr(JSInterfaceJIT::TrustedImm32(8), JSInterfaceJIT::regT3);
</span><span class="cx"> jit.branchSub32(MacroAssembler::NonZero, JSInterfaceJIT::TrustedImm32(1), JSInterfaceJIT::argumentGPR2).linkTo(copyLoop, &jit);
</span><span class="cx">
</span><span class="cx"> // Fill in argumentGPR0 - 1 missing arg slots with undefined
</span><span class="cx"> jit.move(JSInterfaceJIT::argumentGPR0, JSInterfaceJIT::argumentGPR2);
</span><del>- jit.move(JSInterfaceJIT::TrustedImm64(ValueUndefined), JSInterfaceJIT::regT5);
</del><ins>+ jit.move(JSInterfaceJIT::TrustedImm64(ValueUndefined), extraTemp);
</ins><span class="cx"> jit.add32(JSInterfaceJIT::TrustedImm32(1), JSInterfaceJIT::argumentGPR2);
</span><span class="cx"> JSInterfaceJIT::Label fillUndefinedLoop(jit.label());
</span><del>- jit.store64(JSInterfaceJIT::regT5, MacroAssembler::BaseIndex(JSInterfaceJIT::regT3, JSInterfaceJIT::argumentGPR0, JSInterfaceJIT::TimesEight));
</del><ins>+ jit.store64(extraTemp, MacroAssembler::BaseIndex(JSInterfaceJIT::regT3, JSInterfaceJIT::argumentGPR0, JSInterfaceJIT::TimesEight));
</ins><span class="cx"> jit.addPtr(JSInterfaceJIT::TrustedImm32(8), JSInterfaceJIT::regT3);
</span><span class="cx"> jit.branchAdd32(MacroAssembler::NonZero, JSInterfaceJIT::TrustedImm32(1), JSInterfaceJIT::argumentGPR2).linkTo(fillUndefinedLoop, &jit);
</span><span class="cx">
</span><span class="cx"> // Adjust call frame register and stack pointer to account for missing args
</span><del>- jit.move(JSInterfaceJIT::argumentGPR0, JSInterfaceJIT::regT5);
- jit.lshift64(JSInterfaceJIT::TrustedImm32(3), JSInterfaceJIT::regT5);
- jit.addPtr(JSInterfaceJIT::regT5, JSInterfaceJIT::callFrameRegister);
- jit.addPtr(JSInterfaceJIT::regT5, JSInterfaceJIT::stackPointerRegister);
</del><ins>+ jit.move(JSInterfaceJIT::argumentGPR0, extraTemp);
+ jit.lshift64(JSInterfaceJIT::TrustedImm32(3), extraTemp);
+ jit.addPtr(extraTemp, JSInterfaceJIT::callFrameRegister);
+ jit.addPtr(extraTemp, JSInterfaceJIT::stackPointerRegister);
</ins><span class="cx">
</span><span class="cx"> # if CPU(X86_64)
</span><span class="cx"> jit.push(JSInterfaceJIT::regT4);
</span></span></pre>
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