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<dt>Revision</dt> <dd><a href="http://trac.webkit.org/projects/webkit/changeset/160056">160056</a></dd>
<dt>Author</dt> <dd>msaboff@apple.com</dd>
<dt>Date</dt> <dd>2013-12-03 15:56:31 -0800 (Tue, 03 Dec 2013)</dd>
</dl>
<h3>Log Message</h3>
<pre>ARM64: Crash in JIT code due to improper reuse of cached memory temp register
https://bugs.webkit.org/show_bug.cgi?id=125181
Reviewed by Geoffrey Garen.
Changed load8() and load() to invalidate the memory temp CachedTempRegister when the
destination of an absolute load is the memory temp register since the source address
is also the memory temp register. Change branch{8,32,64} of an AbsoluteAddress with
a register to use the dataTempRegister as the destinate of the absolute load to
reduce the chance that we need to invalidate the memory temp register cache.
In the process, found and fixed an outright bug in branch8() where we'd load into
the data temp register and then compare and branch on the memory temp register.
* assembler/MacroAssemblerARM64.h:
(JSC::MacroAssemblerARM64::load8):
(JSC::MacroAssemblerARM64::branch32):
(JSC::MacroAssemblerARM64::branch64):
(JSC::MacroAssemblerARM64::branch8):
(JSC::MacroAssemblerARM64::load):</pre>
<h3>Modified Paths</h3>
<ul>
<li><a href="#trunkSourceJavaScriptCoreChangeLog">trunk/Source/JavaScriptCore/ChangeLog</a></li>
<li><a href="#trunkSourceJavaScriptCoreassemblerMacroAssemblerARM64h">trunk/Source/JavaScriptCore/assembler/MacroAssemblerARM64.h</a></li>
</ul>
</div>
<div id="patch">
<h3>Diff</h3>
<a id="trunkSourceJavaScriptCoreChangeLog"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/ChangeLog (160055 => 160056)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/ChangeLog 2013-12-03 23:54:15 UTC (rev 160055)
+++ trunk/Source/JavaScriptCore/ChangeLog 2013-12-03 23:56:31 UTC (rev 160056)
</span><span class="lines">@@ -1,5 +1,27 @@
</span><span class="cx"> 2013-12-03 Michael Saboff <msaboff@apple.com>
</span><span class="cx">
</span><ins>+ ARM64: Crash in JIT code due to improper reuse of cached memory temp register
+ https://bugs.webkit.org/show_bug.cgi?id=125181
+
+ Reviewed by Geoffrey Garen.
+
+ Changed load8() and load() to invalidate the memory temp CachedTempRegister when the
+ destination of an absolute load is the memory temp register since the source address
+ is also the memory temp register. Change branch{8,32,64} of an AbsoluteAddress with
+ a register to use the dataTempRegister as the destinate of the absolute load to
+ reduce the chance that we need to invalidate the memory temp register cache.
+ In the process, found and fixed an outright bug in branch8() where we'd load into
+ the data temp register and then compare and branch on the memory temp register.
+
+ * assembler/MacroAssemblerARM64.h:
+ (JSC::MacroAssemblerARM64::load8):
+ (JSC::MacroAssemblerARM64::branch32):
+ (JSC::MacroAssemblerARM64::branch64):
+ (JSC::MacroAssemblerARM64::branch8):
+ (JSC::MacroAssemblerARM64::load):
+
+2013-12-03 Michael Saboff <msaboff@apple.com>
+
</ins><span class="cx"> jit/JITArithmetic.cpp doesn't build for non-X86 ports
</span><span class="cx"> https://bugs.webkit.org/show_bug.cgi?id=125185
</span><span class="cx">
</span></span></pre></div>
<a id="trunkSourceJavaScriptCoreassemblerMacroAssemblerARM64h"></a>
<div class="modfile"><h4>Modified: trunk/Source/JavaScriptCore/assembler/MacroAssemblerARM64.h (160055 => 160056)</h4>
<pre class="diff"><span>
<span class="info">--- trunk/Source/JavaScriptCore/assembler/MacroAssemblerARM64.h 2013-12-03 23:54:15 UTC (rev 160055)
+++ trunk/Source/JavaScriptCore/assembler/MacroAssemblerARM64.h 2013-12-03 23:56:31 UTC (rev 160056)
</span><span class="lines">@@ -898,6 +898,8 @@
</span><span class="cx"> {
</span><span class="cx"> moveToCachedReg(TrustedImmPtr(address), m_cachedMemoryTempRegister);
</span><span class="cx"> m_assembler.ldrb(dest, memoryTempRegister, ARM64Registers::zr);
</span><ins>+ if (dest == memoryTempRegister)
+ m_cachedMemoryTempRegister.invalidate();
</ins><span class="cx"> }
</span><span class="cx">
</span><span class="cx"> void load8Signed(BaseIndex address, RegisterID dest)
</span><span class="lines">@@ -1570,8 +1572,8 @@
</span><span class="cx">
</span><span class="cx"> Jump branch32(RelationalCondition cond, AbsoluteAddress left, RegisterID right)
</span><span class="cx"> {
</span><del>- load32(left.m_ptr, getCachedMemoryTempRegisterIDAndInvalidate());
- return branch32(cond, memoryTempRegister, right);
</del><ins>+ load32(left.m_ptr, getCachedDataTempRegisterIDAndInvalidate());
+ return branch32(cond, dataTempRegister, right);
</ins><span class="cx"> }
</span><span class="cx">
</span><span class="cx"> Jump branch32(RelationalCondition cond, AbsoluteAddress left, TrustedImm32 right)
</span><span class="lines">@@ -1608,8 +1610,8 @@
</span><span class="cx">
</span><span class="cx"> Jump branch64(RelationalCondition cond, AbsoluteAddress left, RegisterID right)
</span><span class="cx"> {
</span><del>- load64(left.m_ptr, getCachedMemoryTempRegisterIDAndInvalidate());
- return branch64(cond, memoryTempRegister, right);
</del><ins>+ load64(left.m_ptr, getCachedDataTempRegisterIDAndInvalidate());
+ return branch64(cond, dataTempRegister, right);
</ins><span class="cx"> }
</span><span class="cx">
</span><span class="cx"> Jump branch64(RelationalCondition cond, Address left, RegisterID right)
</span><span class="lines">@@ -1641,7 +1643,7 @@
</span><span class="cx"> Jump branch8(RelationalCondition cond, AbsoluteAddress left, TrustedImm32 right)
</span><span class="cx"> {
</span><span class="cx"> ASSERT(!(0xffffff00 & right.m_value));
</span><del>- load8(left.m_ptr, getCachedDataTempRegisterIDAndInvalidate());
</del><ins>+ load8(left.m_ptr, getCachedMemoryTempRegisterIDAndInvalidate());
</ins><span class="cx"> return branch32(cond, memoryTempRegister, right);
</span><span class="cx"> }
</span><span class="cx">
</span><span class="lines">@@ -2493,6 +2495,9 @@
</span><span class="cx"> intptr_t addressAsInt = reinterpret_cast<intptr_t>(address);
</span><span class="cx"> intptr_t addressDelta = addressAsInt - currentRegisterContents;
</span><span class="cx">
</span><ins>+ if (dest == memoryTempRegister)
+ m_cachedMemoryTempRegister.invalidate();
+
</ins><span class="cx"> if (isInIntRange(addressDelta)) {
</span><span class="cx"> if (ARM64Assembler::canEncodeSImmOffset(addressDelta)) {
</span><span class="cx"> m_assembler.ldur<datasize>(dest, memoryTempRegister, addressDelta);
</span><span class="lines">@@ -2514,7 +2519,10 @@
</span><span class="cx"> }
</span><span class="cx">
</span><span class="cx"> move(TrustedImmPtr(address), memoryTempRegister);
</span><del>- m_cachedMemoryTempRegister.setValue(reinterpret_cast<intptr_t>(address));
</del><ins>+ if (dest == memoryTempRegister)
+ m_cachedMemoryTempRegister.invalidate();
+ else
+ m_cachedMemoryTempRegister.setValue(reinterpret_cast<intptr_t>(address));
</ins><span class="cx"> m_assembler.ldr<datasize>(dest, memoryTempRegister, ARM64Registers::zr);
</span><span class="cx"> }
</span><span class="cx">
</span></span></pre>
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